1、Desaturation Fault Detection Optocoupler Gate Drive Product with Feature: ACPL-332J, ACPL-331J and HCPL-316J Application Note 5324 1. Introduction Desaturation fault detection circuit provides protection for power semiconductor switches (IGBT or MOSFETs) against short-circuit current events which ma
2、y lead to destruction of these power switches. This desaturation of the inverters can also occur due to an insufficient gate drive signal from the inverter gate driver misper- formance or driver supply voltage issues. Other failure modes that can potentially cause excessive currents and excessive po
3、wer dissipations in the inverters can be due to phase and/or rail supply short circuits due to user mis- connect or bad wiring, control signal failures due to noise or computational errors, over load conditions induced by the load, and component failures in the gate drive circuitry. The drastically
4、increased power dissipation very quickly overheats the power inverter and destroys it. To prevent catastrophic damage to the drive, desaturation fault detection and protection must be implemented to reduce or turn-off the overcurrents during the fault condition. This application note covers the desi
5、gn of de- saturation fault detection feature provided by Avago In- telligent Gate Driver. How does desaturation fault detection feature work in Avago driver? i. Fault Detection The IGBT collector-emitter voltage, VCESAT, is monitored by the DESAT pin of the Gate Drive Optocoupler (Pin 14 of Figure 1
6、). When there is short circuit in an application and a very high current flow through the IGBT, it will go into desaturation mode; hence its VCESAT voltage will rise up. A fault is detected by the optocoupler gate driver (while the IGBT is ON) once this VCESAT voltage goes above the internal desatur
7、ation fault detection threshold voltage which is typically 7.0V. This fault detection triggers two events: a. Vout of the optocoupler gate driver is slowly brought low in order to “softly” turn-off the IGBT and prevent large di/dt induced voltage spikes and b. Also activated is an internal feedback
8、channel which brings the Fault output low for the purpose of notifying the micro-controller of the fault condition. At this point, the microcontroller must take the appropriate action to shutdown or reset the motor drive. ii. Soft turn-off This feature exists in Avago gate optocoupler, (e.g. ACPL- 3
9、32J, ACPL-331J and HCPL-316J). When fault is detected by the DESAT feature, a weak pull-down device in the output drive stage will turn on to softly turn off the IGBT and prevents large di/dt induced voltages. This device slowly discharges the IGBT gate to prevent fast changes in collector current t
10、hat could cause damaging voltage spikes due to stray inductances. During the slow turn off, the large output pull-down device remains off until the output voltage falls below V EE+ 2 Volts, at which time the large pull down device clamps the IGBT gate to V EE(Refer to Figure 1). iii. Off State and R
11、eset During the IGBT off state, the driver fault detection circuitry is disabled to prevent false fault signals. The fault output, Pin 3 of Figure 1 is pulled down and output Pin 11 goes low for the duration of the fault. In ACPL-332J and ACPL-331J, the fault is reset at the next positive input sign
12、al to the driver after a fixed mute time. For HCPL- 316J, it has to be reset externally through a Reset pin (Pin 5 of Figure 2). For both case, it will only be cleared when DESAT detection has gone to low (Short-circuit is cleared). iv. Under Voltage Lock-Out protection (UVLO) with hysteresis The Ou
13、tput of the optocoupler gate driver and the FAULT status are controlled by a combination of V IN , UVLO, and the detected IGBT Desat condition. During power up, the UVLO feature prevents the application of insufficient gate voltage to the IGBT, by forcing the output of the optocou- pler gate driver
14、low. Once the power supply of the opto- coupler gate driver are above the positive UVLO thresh- olds the DESAT detection feature is the primary source of the IGBT protection. The output of the optocoupler is safely brought low once the power supply of the op- tocoupler falls below the negative UVLO
15、threshold level. A hysteresis in the Positive UVLO and negative UVLO threshold levels provides an appropriate noise margin for the UVLO detection and output shutdown feature. 2 Figure 1. Desaturation Detection Circuit for ACPL-332J and ACPL-331J. Figure 2. Desaturation Detection Circuit for HCPL-316
16、J 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V E V LED DESAT V CC2 V EE V OUT V CLAMP V EE V S V CC1 FAULT V S CATHODE ANODE ANODE CATHODE R G V CC R DESAT C BLANK D DESAT + _ F 0.1F C F 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V E V LED DESAT V CC2 V EE V OUT V CLAMP V EE V S V CC1 FAULT V S CATHODE ANOD
17、E ANODE CATHODE R G V CC R DESAT C BLANK D DESAT + _ R F 0.1F C F 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V E V LED2+ DESAT V CC2 V C V OUT V EE V EE V IN+ V IN- V CC1 GND1 RESET FAULT V LED1+ V LED1- + _ R G C BLANK , (100pF) Fast Recovery D DESAT Q1 Q2 + V CE - R OPT + HVDC - HVDC 3-PHASE AC + V CE
18、 - 0.1F + _ 0.1F 0.1F 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V E V LED2+ DESAT V CC2 V C V OUT V EE V EE V IN+ V IN- V CC1 GND1 RESET FAULT V LED1+ V LED1- + _ 100 + V CE - + V CE - + _3 2. Basic DESAT detector circuit component selection For typical application, the three external components requir
19、ed to build the DESAT circuit are the DESAT diode, D DESAT , DESAT resistor, R DESATand blank capacitor, C BLANK . Blanking Time The DESAT fault detection circuitry should remain disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the DESAT
20、 threshold. The time period, called the DESAT blanking time ensures that there is no nuisance tripping during IGBT turn-on. This time also represents the time it takes for the driver to a fault condition. The blanking time is controlled by internal DESAT charge current, I CHGof 250 mA (typ), the DES
21、AT voltage threshold, V DESATand the external blank capacitor, C BLANK . During operation, blank capacitor is discharged when driver output is low (IGBT off). That is, the DESAT detection features becomes active only when the output of the gate driver optocoupler is in the high state driving the IGB
22、T in saturation. When the IGBT is turned on, the DESAT capacitor starts charging and protection becomes effective only if the DESAT threshold is exceeded after the blanking time. Blanking Time Capacitor Sizing Blanking time is determined using formula (1): of HCPL-316J, which may respond by generati
23、ng “false” detection signal. In order to minimize this charging current and avoid false DESAT triggering, it is best to use very fast reverse recovery time diodes with very small reverse parasitic capacitance. Listed in the table below are fast-recovery diodes that are suitable for use as a DESAT di
24、ode, DDESAT. The DESAT detection threshold voltage of 7V (typical) can be reduce by placing a string of DESAT diodes in series or place a low voltage zener diode in series. For the string of DESAT diode method, Part Number Manufacturer Trr (ns) Max. Reverse Voltage Rating, VRRM (Volts) Package Type
25、ERA34-10 Fuji Semiconductor 15 1000 Axial Leaded MUR1100E Motorola 75 1000 59-04 (Axial leaded) UF4007 General Semi. 75 1000 DO-204AL (Axial leaded) BYM26E Philips 75 1000 SOD64 (axial leaded) BYV26E Philips 75 1000 SOD57 (axisal leaded) BYV99 Philips 75 600 SOD87 (surface mount) MURS160T3 Motorola
26、75 600 Case 403A (Surface Mt) (1) * CHG DESAT BLANK BLANK I V C t = The recommended value is 100pF which gives a blank time of 2.6s (Condition: I CHG= 250 mA and V DESAT= 6.5V; Page 9 of HCPL-316J datasheet AV01-0579EN). HV Blocking Diode and DESAT Threshold The DESAT diode function is to conduct fo
27、rward current, allowing sensing of IGBTs V CESAT . In high power ap- plication, DESAT pin may be pulled low due to reverse recovery spikes of the freewheeling diode. This reverse recovery spike tend to forward bias the substrate diode (2) ) ( F Threshold New DESAT V = 7.0 - n * V (3) ) ( Z F Thresho
28、ld New DESAT V V - = 7.0 - V For the DESAT diode with Zener Diode method, where n is the number of DESAT diodes, Vz is the zener voltage value and V fis the forward votlage of DESAT diode. This allow the designer to choose the appropriate threshold voltage. DESAT Resistor The anti-parallel diode of
29、the IGBT can have a large in- stantaneous forward voltage transient which exceeds the nominal forward voltage of the diode. This may result in large negative voltage spike on the DESAT pin which will draw a substantial amount of current out of the driver. To limit the current level drawn from the ga
30、te driver, a DESAT resistor can be added (100 recommended) in series with the DESAT diode. The added resistor will not appreciably alter the DESAT threshold or the blanking time. FAULT Output Pin The FAULT pin (Pin 3 of ACPL-332J/331J and Pin 6 of HCPL-316J) is an open collector output and requires
31、a pull-up resistor, RF (2.1k for ACPL-332J and 331J, 3.3 k for HCPL-316J) to provide a high level signal. In order to prevent the FAULT pin from being “triggered” by high CMR noise, a filter capacitor, CF is included between FAULT pin and ground (Figure 1).4 3. Advanced desaturation detection topic
32、Internal Charging Current Source Wide Variation, I CHGThe “blanking capacitor charge current” parameter in the data sheet (page 9 of HCPL-316J datasheet), its values are listed as: Blanking Capacitor Charging Current, I CHG Min Typ Max Units 130 250 330 mA Based on 7V desaturation voltage threshold
33、and the above charging current, we will get three different blanking time; minimum, typical and maximum value. For some application, this variation may not be a problem. However, to minimize the above variation, several external blanking circuits are suggested in this Application Note. These are sho
34、wn in figures 3, 4 and 5. Prevent False Fault Detection Due to Negative Voltage Spikes during Power Semiconductor Switching Operation One of the situations that may cause the driver to generate a false fault signal is if the substrate diode of the driver is forward biased. This can happen if the rev
35、erse recovery spikes coming from the IGBT free wheeling diodes bring the DESAT pin below ground. Hence the DESAT pin voltage will be brought above the threshold voltage. This negative going voltage spikes is typically generated by inductive loads or reverse recovery spikes of the IGBT/MOSFETs free-w
36、heeling diodes. In order to prevent false fault signal, it is highly recom- mended to connect a zener diode and schottky diode across DESAT pin and VE pin (e.g. for HCPL-316J, between pin 14 and 16). This circuit solution is shown in Figure 3. The schottky diode will prevent the substrate diode of t
37、he gate driver optocoupler from being forward biased while the zener diode (Value around 7.5 to 8V) is used to prevent any positive high transient voltage to affect the DESAT pin. (3) * t V C I CHG = A A V pF t 5.38 130 7 * 100 (max) = = A A V pF t 2.8 250 7 * 100 (typ) = = A A V pF t 2.12 330 7 * 1
38、00 (min) = = Using the above formula, the I CHG , C BLANK= 100pF (Figure 1) and V=7V, we will have the following blanking time, Other Methods of Tweaking DESAT detection Blanking time Besides the recommended circuit to adjust blanking time in Figure 1 and 2, two other methods are introduced in this
39、application note. The first method shown in Figure 3 and 4 uses additional capacitors, resistor and a FET. The second simpler method shown in Figure 5 requires only one additional resistor plus scaling of the blanking capacitor, CBLANK. The figures show how this can be connected using HCPL-316J. Thi
40、s circuitry is applicable with other similar drivers like ACPL-332J. In Figure 3 and 4, the blanking time is controller by Q1 with time constant adjusted by capacitor value of 680pF and resistor 1kohm. Designers may choose to adjust this value according to their desired blanking time. The 4*RC time
41、constant with 680pF and 1 k provide for a blanking time of 2.7 s. Figure 5 shows another concept for an external blanking circuit. This method uses one additional external resistor RB connected from the output to the DESAT pin. This allows an additional blanking capacitor charging current component
42、from the output of the gate driver optocou- pler through RB and adds to the internal current source of the gate drive optocoupler. This higher blanking capacitor charging current allows a designer greater flexibility in choosing both an appropriate value of the blanking capacitor and an appropriate
43、current through a choice of the external resistor RB. By adjusting the capacitance of the blanking capacitor and the addi- tional current through RB a designer can set a specific precise blanking time, and an example calculation of the blanking time is shown below: ) 1 ( ) ( RC t f i C e V V t V - -
44、 - = Conditions areV EE= 9VV CC2= 17VR B= 1000kohmC BLANK= 4700pF At t= 0, At t= infinity, V V V f i C ) ( = - 9 + 26 = 17 V + = V V i C ) ( = - 9 V = 05 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V E V LED2+ DESAT V CC2 V C V OUT V EE V EE V IN+ V IN- V CC1 GND1 RESET FAULT V LED1+ V LED1- + _ R G 100
45、100pF Fast Recovery D DESAT Q1 Q2 + V CE - R OPT + HVDC - HVDC 3-PHASE AC + V CE - 0.1F + _ 680pF 0.1F 680pF 1k MBR0540 Schottky Diode 10V Zener 1N5925A External Blanking Circuit Protection on DESAT Pin 14 16 Q1 TMOS 2N7002LT1 0.1uF C2 C1 R1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V E V LED2+ DESAT V
46、 CC2 V C V OUT V EE V EE V IN+ V IN- V CC1 GND1 RESET FAULT V LED1+ V LED1- + _ + V CE - R OPT + V CE - + _ 0.1 Figure 3. External blanking circuit with 2.5s nominal blanking delay using HCPL-316J Hence, where t = tblank and Vc(tblank) = 7V (base of HCPL-316J threshold voltage) With R B= 1000, C BLA
47、NK= 4700pF ) 1 ( ) ( RC t f i C e V V t V - - + = ) (t) = - 9 + 26 (1 - e RC t C V - = 4.5 s t BLANK 26 16 = 0.3846 = 1 - - RC t BLANK e ) 7 = - 9 + 26 (1 = e RC t BLANK = = ln(0.3846) - RC t BLANKFigure 4. External blanking circuit with external buffer for high current drive using HCPL-316J 1 2 3 4
48、 5 6 7 8 16 15 14 13 12 11 10 9 V E V LED2+ DESAT V CC2 V C V OUT V EE V EE V IN+ V IN- V CC1 GND1 RESET FAULT V LED1+ V LED1- + _ R G 100 100pF Fast Recovery D DESAT Q1 Q2 + V CE - R OPT + V CE - 0.1F + _ 680pF 0.1F 680pF 1k 14 16 0.1uF 2.5 10nF C2 C1 R1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V E V
49、 LED2+ DESAT V CC2 V C V OUT V EE V EE V IN+ V IN- V CC1 GND1 RESET FAULT V LED1+ V LED1- R G + V CE - + V CE - 0.1 + _ 0.1 680pF 0.1uF 4.5 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V E V LED2+ DESAT V CC2 V C V OUT V EE V EE V IN+ V IN- V CC1 GND1 RESET FAULT V LED1+ V LED1- + V CE - + HVDC - HVDC 3-PHASE AC + V CE - + _ MBR0540 Schottky Diode 10V Zener 1N5925A External Blanking Circuit Protection on DESAT Pin Q1 TMOS 2N7002LT1 Figure 5. Second Method of External Blanking Circuit using HCPL-316J Blanking Circuit 1 2 3 4 5 6 7 8 16 15 14 13 12 11 1
