1、基于ISE14.7的Fpga基础教程,BVT Zero Liu,content,What is the FPGAFPGA design flowProject environment：ISE 14.7Verilog examplesFunctional simulationProgram and debug,WHAT IS the FPGA,Part of the Graphite circuit,What can FPGA do?,FPGA: Field Programmable Gate array PLD: Programmable Logic Device CPLD: Complex
2、Programmable Logic Device,WHAT IS the FPGA,I/O: pins connected to peripheral circuit PLL: frequency multiplication, frequency demultiplication and phase shift MUTIPLIER M4K BLOCK:Memory block, for RAM ROM and FIFO design LOGIC ARRAYFor combinatory logic and trigger design Program and debug block:,St
3、ructure of FPGA,WHAT IS the FPGA,Summary of spartan-3A FPGA attributes,NOTE CLB: configurable logic block DCM: digital clock manager,Device utilization of Graphite FPGA(XC3S400A),FPGA DESIGN FLOWimplementation,ISE,Functional description Reference to hw spec. &FPGA spec. Design input Schematic or HDL
4、(RTL) Pin assignment Planner or TCL script Synthesis Output gate-level netlist based on some kind of FPGA Logical description to specific devices Place & routeDownload and verify,FPGA DESIGN FLOWverification,Three key verification points for FPGA implementation Behavioral simulation Post-place & rou
5、te static timing analysis Download and verify in circuitPost-synthesis gate-level simulation and post-place & route timing simulations can be done for production sign off Post-place & route timing simulations are also often done to verify board- and system-level timing,7,IDE ( integrated development
6、 environment )THE MAIN INTERFACE OF ISE14.7,Design Spec. and process,BVT FPGA design process,Reference Documents: HW spec. Schematic FPGA spec. FPGA design process,Graphite documents,1, Create a new project,2, Project name, location and source type,3, Chose device and tools,IDE: create a new project
7、,4, Finish,IDE A new project,ide Create/add new source,IDE A completed project,project files (*.v),模块开始和结束（figure 1） 变量声明（figure 2） 数据流语句 低层模块实例（figure3） 行为描述块 任务和函数,Figure 1,Figure 3,Figure 2,Verilog standardpurpose,Purpose: Less space Higher sanitary Easy to analyze and debug Easy to read and unde
8、rstand Portability,Verilog standardStandardized design,结构层次化,命名规范化,常量参数化,其他,Clock：避免混合时钟，避免门控时钟，单模块单时钟 Reset：避免模块内部产生 Always：敏感变量完备化,project files（*.ucf）,Schematic view,Step1: view schematic,Step2: choose start up,Schematic view,Choose elements to create schematic,Schematic view,Graphite signal: ,Fu
9、nctional simulation,Functional simulation,Functional simulation,Simulation tool：isim,Graphite：PID_LED_CONTROL simulation,Reference documents,Figure: LED control, from Graphite schematic,Figure: led behavior description, from Graphite FPGA spec.,Simulation tool：isim,Graphite：reset timing simulation,P
10、rogram and debug compile,Failed,successful,Program and degub start impact,impactselect/add storage device,impactgenerating prom file,*.mcs file,*.xsvf file,Download and program,JTAG chain scanning,Download and program,Choose the programmable image,Download and program,Program,Verify it on your board!,Thanks!,
