1、 CONFIDENTIAL ADVANCE INFORMATION ES9023 Datasheet ESS TECHNOLOGY , INC. 48401 Fremont Blvd., Fremont, CA 94538, USA Tel (510) 492-1088 Fax (510) 492-1098 FEATURE BENEFIT Sabre DAC and 2Vrms op-amp driver integration Lowest system cost by minimizing external components Highest performance Best sound
2、ing audio powered by Sabre DAC technology Patented HyperStream TMand Jitter Elimination Architecture Best dynamic range: 112dB Jitter Immune Adjustable output level Allow designer to customize output level (up to 2Vrms) based on application requirements via an external resistor Ground reference outp
3、ut Reduce cost by eliminating blocking capacitors Pop-noise suppression Pop-free on power up/down, mute and reset Dedicated control/status pins I2S or left-justified select Soft mute enable Zero detect output Easy to use no programming required Charge pump for negative supply Single AVCC simplifies
4、power supply Low power consumption in 16-SOP Simply power supply and reduce PCB size Device Description DNR (dB) Power Supply (Output Level) No DC-blocking capacitor Pop-Noise Free Package ES9023 Sabre Premier Stereo DAC with 2Vrms Op-Amp Driver 112 +3.6V (2Vrms) +3.3V (1.9Vrms) 16-SOP The ES9023 is
5、 a 24-bit stereo audio DAC with an integrated 2Vrms op-amp driver. Powered by the industry proven Sabre DAC technology, the ES9023 combines best-sounding audio with lowest system cost and highest performance into the ideal D/A converter for line-level output applications such as Blu-ray players, CD/
6、DVD players, set-top boxes, digital TVs and audio receivers. With patented Hyperstream TMarchitecture and Time Domain Jitter Eliminator, the ES9023 delivers jitter-free studio quality audio with 112dB DNR. Using an integrated charge pump to generate the negative supply, the ES9023 can operate from a
7、 single AVCC supply to drive a ground-referenced 2Vrms output, eliminating the need for output dc-blocking capacitors. Optionally, the output level can be adjusted by using an external resistor, allowing for output level below 2Vrms. Pop-noise is eliminated through a comprehensive suppression on pow
8、er up/down, mute, reset, loss of power or clock. Dedicated control/status pins allow easy system integration without the need for microcontroller programming. Confidential - Shaw Electronics CONFIDENTIAL ADVANCE INFORMATION Rev. 0.1 September 17, 2010 ES9023 Datasheet ESS TECHNOLOGY , INC. 48401 Fre
9、mont Blvd., Fremont, CA 94538, USA Tel (510) 492-1088 Fax (510) 492-1098 2 FUNCTIONAL BLOCK DIAGRAM APPLICATION DIAGRAM PCM Interface Jitter Reduction Oversampling Filter Control/Status Power Supply & Charge Pump HyperStream DAC (2x) HyperStream DAC (2x) BCK AVDD AVSS ES9023 2Vrms Op-Amp Driver (2x)
10、 LRCK SDI MCLK AOUTL AOUTR VEE CP CN L Audio Processor ES9023 R Audio Out (2Vrms) 3.3V Blu-Ray Player DVD Player Home Theater Receiver PC Pro-Audio Sound Card Confidential - Shaw Electronics September 17, 2010 CONFIDENTIAL ADVANCE INFORMATION Rev. 0.1 ES9023 Datasheet3 ESS TECHNOLOGY , INC. 48401 Fr
11、emont Blvd., Fremont, CA 94538, USA Tel (510) 492-1088 Fax (510) 492-1098 PIN LAYOUT BCK 1 16 ZD LRCK 2 15 MUTE_B SDI 3 14 DGND DIF 4 ES9023 13 MCLK AVCC 5 16SOP 12 AGND VREG 6 11 NEG AOUTL 7 10 CN AOUTR 8 9 CPPIN DESCRIPTION Pin # Name Type Pin Description 1 BCK I I2S Bit Clock 2 LRCK I I2S L/R (Wo
12、rd) Clock 3 SDI I I2S Serial Data Input 4 DIF I Input to select Left Justified or I2S data 5 AVCC P AVCC Power supply 6 VREG P Analog Reference Output 7 AOUTL O Left Analog Output 8 AOUTR O Right Analog Output 9 CP I Positive Terminal of External Charge Pump Capacitor 10 CN I Negative Terminal of Ex
13、ternal Charge Pump Capacitor 11 NEG P Negative Supply (Internally Generated) 12 AGND P Analog Ground 13 MCLK I Master (System) Clock 14 DGND P Ground 15 MUTE_B I Active Low Mute Input 16 ZD O Zero Detect Output Confidential - Shaw Electronics CONFIDENTIAL ADVANCE INFORMATION Rev. 0.1 September 17, 2
14、010 ES9023 Datasheet ESS TECHNOLOGY , INC. 48401 Fremont Blvd., Fremont, CA 94538, USA Tel (510) 492-1088 Fax (510) 492-1098 4 FUNCTIONAL DESCRIPTION I2S Decoder: Run by the I2S bit clock, typically a 64FS clock, the I2S Decoder translates the incoming I2S data to 24-bit signed PCM data. If a smalle
15、r bit-width is used, the remaining is zero-padded. Driving the DIF pin low will set the DAC in I2S mode while driving the pin high will set the DAC in LJ mode. Below is a timing diagram illustrating the two modes (LJ and I2S) utilized by the ES9023. Zero Detect: The zero-detect function outputs an e
16、xternal status signal (ZD) based on a zero-valued input for a given number of clock cycles. The ZD output signal is set high when both data channels are zero for 8192 LRCK cycles. MCLK Asynchronous mode: MCLK must be 192*fs. Synchronous mode: Please see table below for supported configurations. LRCK
17、 (kHz) MCLK (MHz) fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 32 - - - 12.288 16.384 24.576 36.864 44.1 - - 11.2896 16.9344 22.5792 33.8688 - 48 - - 12.288 18.432 24.576 36.864 - 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 - - 96 12.288 18.432 24.576 36.864 49.152 - - 176.4 22.5792 33.8688 45.158
18、4 - - - - 192 24.576 36.864 49.152 - - - - For best performance. 256fs or greater is recommended for 32kHz to 96kHz sampling. Confidential - Shaw Electronics September 17, 2010 CONFIDENTIAL ADVANCE INFORMATION Rev. 0.1 ES9023 Datasheet5 ESS TECHNOLOGY , INC. 48401 Fremont Blvd., Fremont, CA 94538, U
19、SA Tel (510) 492-1088 Fax (510) 492-1098 MUTE_B Pin (Active Low) This input pin provides the ability to slowly ramp down the audio volume, and then enter low power standby. Release of mute will cause the ES9023 to emerge from low power mode and then slowly ramp the audio to provide a pop free startu
20、p. MUTE_B (Internal) Attenuation 0dB - 2097024 MCLK AOUT 2097024 MCLK (Internal) Power Down Power up delay 32768 MCLKActivation/release of the MUTE_B input pin initiates a sequence of internal events detailed below: On assertion of the MUTE_B pin o The output signal will ramp to the - level. The ram
21、ping takes 2097024 MCLK cycles. o After the output signal reaches the - level, analog section is turned off and the ES9023 enters a low power standby state. On release of the MUTE_B pin: o The ES9023 emerges from low power standby, starts an internal counter and activates the analog section o During
22、 the delay counter time, the internal charge pump and Vref stabilize. o When the counter reaches 32768 MCLK cycles, the audio signal is applied and the volume is ramped over 2097024 MCLK cycles to maximum. To minimize pop noise at power up, an external circuit should be used to hold the MUTE_B pin a
23、sserted until t DMUTE(see p.10) after the power supply and MCLK are stabilized. This can be realized using a reset IC, an MCU GPIO pin (default to low at power-up and changed to high by software later), or an RC time delay on this pin. If MUTE_B pin is released too early, pop noise may occur due to
24、the ramp-up of internal voltage. AVCC MCLK MUTE_B mm! Confidential - Shaw Electronics CONFIDENTIAL ADVANCE INFORMATION Rev. 0.1 September 17, 2010 ES9023 Datasheet ESS TECHNOLOGY , INC. 48401 Fremont Blvd., Fremont, CA 94538, USA Tel (510) 492-1088 Fax (510) 492-1098 6 DAC/OP-AMP: Each Hyperstream D
25、AC is followed by an op-amp circuit for each channel. A pop suppression circuit is added on the output to eliminate any “pop” noise that may be heard during muting, un-muting, power-up and power-down sequences. In some conditions, pop noise may be audible. See the MUTE_B pin section above. Charge Pu
26、mp (Negative Voltage Generation): This is an analog circuit required to generate an internal negative supply. With positive and negative supplies, the op-amp circuits will be able to generate a ground-referenced 2Vrms output. Confidential - Shaw Electronics September 17, 2010 CONFIDENTIAL ADVANCE IN
27、FORMATION Rev. 0.1 ES9023 Datasheet7 ESS TECHNOLOGY , INC. 48401 Fremont Blvd., Fremont, CA 94538, USA Tel (510) 492-1088 Fax (510) 492-1098 APPLICATION DIAGRAM R 8 : see p.9 for more details. 10uF ES9023 100k 2.2uF GNDConfidential - Shaw Electronics CONFIDENTIAL ADVANCE INFORMATION Rev. 0.1 Septemb
28、er 17, 2010 ES9023 Datasheet ESS TECHNOLOGY , INC. 48401 Fremont Blvd., Fremont, CA 94538, USA Tel (510) 492-1088 Fax (510) 492-1098 8 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PAREMETER RATING Storage temperature -65 C to 105 C Voltage range for 5V tolerant pins -0.5V to +5.5V Voltage rang
29、e for all other pins -0.5V to (AVCC+0.5V) WARNING: Stress beyond those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended O
30、perating Conditions section of this specification is not implied. Exposure to the Absolute Maximum Ratings conditions for extended periods may affect device reliability. WARNING: Electrostatic Discharge (ESD) can damage this device. Proper procedures must be followed to avoid ESD when handling this
31、device. RECOMMENDED OPERATING CONDITIONS PAREMETER SYMBOL CONDITIONS Operating temperature TA 0 C to 70 C Power supply voltage AVCC 3.6V 5%, 31 mA nominal (*1), or 3.3V 5%, 23 mA nominal (*1) Note (*1) fs =48kHz, MCLK=27MHz, I2S input, output unloaded DC ELECTRICAL CHARACTERISTICS Table 1 DC Electri
32、cal Characteristics SYMBOL PARAMETER MIN MAX UNIT COMMENTS 2 AVCC V All inputs TTL levels except CLK and 5V tolerant input pins V IHHigh-level input voltage 2 5.5 V All 5V tolerant inputs V ILLow-level input voltage -0.3 0.8 V All input TTL levels except CLK V CLKHCLK high-level input 2 AVCC+0.25 V
33、V CLKLCLK low-level input -0.3 0.8 V TTL level input V OHHigh-level output voltage 3 V I OH = 1mA V OLLow-level-output voltage 0.45 V I OL =4mA I LIInput leakage current 15 I LOOutput leakage current 15 m A C INInput capacitance 10 C OInput/output capacitance 12 pF fc = 1MHz C CLKCLK capacitance 20
34、pF fc = 1MHz Confidential - Shaw Electronics September 17, 2010 CONFIDENTIAL ADVANCE INFORMATION Rev. 0.1 ES9023 Datasheet9 ESS TECHNOLOGY , INC. 48401 Fremont Blvd., Fremont, CA 94538, USA Tel (510) 492-1088 Fax (510) 492-1098 MCLK Timing t MCH t MCL t MCY MCLK t MCH t MCL t MCY MCLKParameter Symbo
35、l Min Max Unit MCLK pulse width high T MCH9 ns MCLK pulse width low T MCL9 ns MCLK cycle time T MCY20 ns MCLK duty cycle 45:55 55:45 Audio Interface Timing t DCH t DCL t DCY DATACLK t DH t DS DATA8:1 Valid Invalid Invalid t DCH t DCL t DCY DATACLK t DH t DS DATA8:1 Valid Invalid Invalid BCK SDI/LRCK
36、 Parameter Symbol Min Max Unit BCK pulse width high t DCH20 ns BCK pulse width low t DCL20 ns BCK cycle time t DCY44 ns BCK duty cycle 45:55 55:45 SDI/LRCK set-up time to BCK rising edge t DS2 ns SDI/LRCK hold time to BCK rising edge t DH2 ns Confidential - Shaw Electronics CONFIDENTIAL ADVANCE INFO
37、RMATION Rev. 0.1 September 17, 2010 ES9023 Datasheet ESS TECHNOLOGY , INC. 48401 Fremont Blvd., Fremont, CA 94538, USA Tel (510) 492-1088 Fax (510) 492-1098 10 ANALOG PERFORMANCE Test Conditions (unless otherwise stated) 1. T A =25 o C, AVCC=3.6V, fs =44.1kHz, MCLK=27Mhz, 24-bit data, R L 10kW , Sig
38、nal Frequency=1kHz 2. SNR/DNR: A-weighted over 20-22kHz in averaging mode 3. THD+N: un-weighted over 20-22kHz bandwidth PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT PCM sampling rate f S200 kHz Mute Delay t DMUTE500 mS DYNAMIC PERFORMANCE DNR (A-weighted) -60dBFS 112 dB-A 0dBFS 0.002 0.006 % THD+N -
39、3dBFS 0.005 % Interchannel Isolation 100 dB DC Accuracy Absolute DC Offset 4 mV 0dBFS, AVCC=3.6V, R 8 =130kW 2.0 Vrms Output Voltage V O0dBFS, AVCC=3.3V, R 8 =220kW 1.9 Vrms Load Resistance R L5 kW Digital Filter Performance 0.005dB 0.454 fs Pass band -3dB 0.49 fs Stop band -115dB 0.546 dB Group Del
40、ay 35/fs S V O (V rms ) R C = 2.2 R 8 (kW ) 1.8 Select R 8 130kW for no clipping 2V AVCC=3.6VV O (V rms ) R C = 2 R 8 (kW ) 1.6 1.9V AVCC=3.3V Select R 8 220kW for no clippingConfidential - Shaw Electronics September 17, 2010 CONFIDENTIAL ADVANCE INFORMATION Rev. 0.1 ES9023 Datasheet11 ESS TECHNOLOG
41、Y , INC. 48401 Fremont Blvd., Fremont, CA 94538, USA Tel (510) 492-1088 Fax (510) 492-1098 16 Pin SOP Mechanical Dimensions The solder paste and PCB finish/plating must be 100% lead-free in order to ensure proper solderability. Confidential - Shaw Electronics CONFIDENTIAL ADVANCE INFORMATION Rev. 0.
42、1 September 17, 2010 ES9023 Datasheet ESS TECHNOLOGY , INC. 48401 Fremont Blvd., Fremont, CA 94538, USA Tel (510) 492-1088 Fax (510) 492-1098 12 Reflow Process Considerations For lead-free soldering, the characterization and optimization of the reflow process is the most important factor you need to
43、 consider. The lead-free alloy solder has a melting point of 217 C. This alloy requires a minimum reflow temperat ure of 235 C to ensure good wetting. The maximum reflow temperature is in the 245 C to 260 C range, depending on the package size (Table RPC- 2). This narrows the process window for lead
44、-free soldering to 10 C to 20 C. The increase in peak reflow temperature in combination with the narrow process window makes the development of an optimal reflow profile a critical factor for ensuring a successful lead-free assembly process. The major factors contributing to the development of an op
45、timal thermal profile are the size and weight of the assembly, the density of the components, the mix of large and small components, and the paste chemistry being used. Reflow profiling needs to be performed by attaching calibrated thermocouples well adhered to the device as well as other critical l
46、ocations on the board to ensure that all components are heated to temperatures above the minimum reflow temperatures and that smaller components do not exceed the maximum temperature limits (Table RPC-2). To ensure that all packages can be successfully and reliably assembled, the reflow profiles stu
47、died and recommended by ESS are based on the JEDEC/IPC standard J-STD-020 revision D.1. Figure RPC-1. IR/Convection Reflow Profile (IPC/JEDEC J-STD-020D.1) Confidential - Shaw Electronics September 17, 2010 CONFIDENTIAL ADVANCE INFORMATION Rev. 0.1 ES9023 Datasheet13 ESS TECHNOLOGY , INC. 48401 Frem
48、ont Blvd., Fremont, CA 94538, USA Tel (510) 492-1088 Fax (510) 492-1098 Table RPC-1 Classification reflow profile Profile Feature Pb-Free Assembly Preheat/Soak Temperature Min (Tsmin) Temperature Max (Tsmax) Time (ts) from (Tsmin to Tsmax) 150 C 200 C 60-120 seconds Ramp-up rate (TL to Tp) 3 C/secon
49、d max. Liquidous temperature (TL) Time (tL) maintained above TL 217 C 60-150 seconds Peak package body temperature (Tp) For users Tp must not exceed the classification temp in Table RPC-2. For suppliers Tp must equal or exceed the Classification temp in Table RPC-2. Time (tp)* within 5 C of the speci
