1、W25Q128FV Publication Release Date: October 09, 2013 Revision H1 3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI W25Q128FV - 1 - Table of Contents 1. GENERAL DESCRIPTIONS . 5 2. FEATURES . 5 3. PACKAGE TYPES AND PIN CONFIGURATIONS . 6 3.1 Pin Configuration SOIC / VSOP 208-mil 6 3.2 Pad Conf
2、iguration WSON 6x5-mm / 8x6-mm. 6 3.3 Pin Description SOIC / VSOP 208-mil, WSON 6x5-mm / 8x6-mm 6 3.4 Pin Configuration SOIC 300-mil . 7 3.5 Pin Description SOIC 300-mil . 7 3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) . 8 3.7 Ball Description TFBGA 8x6-mm 8 3.8 Pin Configuration PDIP
3、 300-mil 9 3.9 Pin Description PDIP 300-mil . 9 4. PIN DESCRIPTIONS . 10 4.1 Chip Select (/CS) 10 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) 10 4.3 Write Protect (/WP) . 10 4.4 HOLD (/HOLD) . 10 4.5 Serial Clock (CLK) 10 4.6 Reset (/RESET) 10 5. BLOCK DIAGRAM . 11 6. FUNCT
4、IONAL DESCRIPTIONS . 12 6.1 SPI / QPI Operations 12 6.1.1 Standard SPI Instructions . 12 6.1.2 Dual SPI Instructions 12 6.1.3 Quad SPI Instructions . 13 6.1.4 QPI Instructions 13 6.1.5 Hold Function . 13 6.1.6 Software Reset & Hardware /RESET pin 15 6.2 Write Protection 16 6.2.1 Write Protect Featur
5、es 16 7. STATUS AND CONFIGURATION REGISTERS 17 7.1 Status Registers . 17 7.1.1 Erase/Write In Progress (BUSY) Status Only 17 7.1.2 Write Enable Latch (WEL) Status Only 17 7.1.3 Block Protect Bits (BP2, BP1, BP0) Volatile/Non-Volatile Writable 17 W25Q128FV Publication Release Date: October 09, 2013 -
6、 2 - Revision I 7.1.4 Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable . 18 7.1.5 Sector/Block Protect Bit (SEC) Volatile/Non-Volatile Writable . 18 7.1.6 Complement Protect (CMP) Volatile/Non-Volatile Writable 18 7.1.7 Status Register Protect (SRP1, SRP0) Volatile/Non-Volatile Writable
7、. 18 7.1.8 Erase/Program Suspend Status (SUS) Status Only 19 7.1.9 Security Register Lock Bits (LB3, LB2, LB1) Volatile/Non-Volatile OTP Writable 19 7.1.10 Quad Enable (QE) Volatile/Non-Volatile Writable. 19 7.1.11 Write Protect Selection (WPS) Volatile/Non-Volatile Writable 20 7.1.12 Output Driver
8、Strength (DRV1, DRV0) Volatile/Non-Volatile Writable 20 7.1.13 HOLD or /RESET Pin Function (HOLD/RST) Volatile/Non-Volatile Writable 20 7.1.14 Reserved Bits Non Functional 21 7.1.15 W25Q128FV Status Register Memory Protection (WPS = 0, CMP = 0) . 22 7.1.16 W25Q128FV Status Register Memory Protection
9、 (WPS = 0, CMP = 1) . 23 7.1.17 W25Q128FV Individual Block Memory Protection (WPS=1) . 24 8. INSTRUCTIONS 25 8.1 Device ID and Instruction Set Tables . 25 8.1.1 Manufacturer and Device Identification . 25 8.1.2 Instruction Set Table 1 (Standard/Dual/Quad SPI Instructions) (1). 26 8.1.3 Instruction S
10、et Table 2 (Standard/Dual/Quad SPI Instructions) (1). 27 8.1.4 Instruction Set Table 3 (QPI Instructions) (14). 28 8.2 Instruction Descriptions 30 8.2.1 Write Enable (06h) 30 8.2.2 Write Enable for Volatile Status Register (50h). 30 8.2.3 Write Disable (04h) . 31 8.2.4 Read Status Register-1 (05h),
11、Status Register-2 (35h) & Status Register-3 (15h) . 31 8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) . 32 8.2.6 Read Data (03h) . 35 8.2.7 Fast Read (0Bh) . 36 8.2.8 Fast Read Dual Output (3Bh) . 38 8.2.9 Fast Read Quad Output (6Bh) 39 8.2.10 Fast Read Dual I
12、/O (BBh) . 40 8.2.11 Fast Read Quad I/O (EBh) 42 8.2.12 Word Read Quad I/O (E7h) . 45 8.2.13 Octal Word Read Quad I/O (E3h) . 47 8.2.14 Set Burst with Wrap (77h) . 49 8.2.15 Page Program (02h) 50 8.2.16 Quad Input Page Program (32h) . 52 8.2.17 Sector Erase (20h) 53 8.2.18 32KB Block Erase (52h) 54
13、8.2.19 64KB Block Erase (D8h) . 55 W25Q128FV - 3 - 8.2.20 Chip Erase (C7h / 60h) . 56 8.2.21 Erase / Program Suspend (75h) 57 8.2.22 Erase / Program Resume (7Ah) 59 8.2.23 Power-down (B9h) . 60 8.2.24 Release Power-down / Device ID (ABh) 61 8.2.25 Read Manufacturer / Device ID (90h) 63 8.2.26 Read M
14、anufacturer / Device ID Dual I/O (92h) 64 8.2.27 Read Manufacturer / Device ID Quad I/O (94h) 65 8.2.28 Read Unique ID Number (4Bh) . 66 8.2.29 Read JEDEC ID (9Fh) . 67 8.2.30 Read SFDP Register (5Ah) . 68 8.2.31 Erase Security Registers (44h) . 69 8.2.32 Program Security Registers (42h) . 70 8.2.33
15、 Read Security Registers (48h) 71 8.2.34 Set Read Parameters (C0h) 72 8.2.35 Burst Read with Wrap (0Ch) . 73 8.2.36 Enter QPI Mode (38h) . 74 8.2.37 Exit QPI Mode (FFh) . 75 8.2.38 Individual Block/Sector Lock (36h) 76 8.2.39 Individual Block/Sector Unlock (39h) . 77 8.2.40 Read Block/Sector Lock (3
16、Dh) 78 8.2.41 Global Block/Sector Lock (7Eh) 79 8.2.42 Global Block/Sector Unlock (98h) . 79 8.2.43 Enable Reset (66h) and Reset Device (99h) . 80 9. ELECTRICAL CHARACTERISTICS . 81 9.1 Absolute Maximum Ratings(1)(2)81 9.2 Operating Ranges . 81 9.3 Power-Up Power-Down Timing and Requirements (1). 82
17、 9.4 DC Electrical Characteristics 83 9.5 AC Measurement Conditions (1). 84 9.6 AC Electrical Characteristics (6). 85 AC Electrical Characteristics (contd) . 86 9.7 Serial Output Timing . 87 9.8 Serial Input Timing 87 9.9 HOLD Timing 87 9.10 WP Timing 87 10. PACKAGE SPECIFICATIONS . 88 10.1 8-Pin SO
18、IC 208-mil (Package Code S) 88 10.2 8-Pin VSOP 208-mil (Package Code T) . 89 W25Q128FV Publication Release Date: October 09, 2013 - 4 - Revision I 10.3 8-Pin PDIP 300-mil (Package Code A) . 90 10.4 8-Pad WSON 6x5-mm (Package Code P) . 91 10.5 8-Pad WSON 8x6-mm (Package Code E) . 92 10.6 16-Pin SOIC
19、300-mil (Package Code F) 93 10.7 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 ball array) 94 10.8 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 ball array) . 95 11. ORDERING INFORMATION 96 11.1 Valid Part Numbers and Top Side Marking 97 12. REVISION HISTORY 98 W25Q128FV - 5 - 1. GENERAL DESCRIPTIONS The
20、W25Q128FV (128M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP)
21、 and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1A for power-down. All devices are offered in space- saving packages. The W25Q128FV array is organized into 65,536 programmable pages of 256-bytes each. Up t
22、o 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128FV has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors al
23、low for greater flexibility in applications that require data and parameter storage. (See Figure 2.) The W25Q128FV support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2-clocks instruction cycle Quad Peripheral Interface (QPI): Serial Clock, Chip Select, Serial Data I
24、/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O and QPI instructions. These transfer rates can outper
25、form standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write
26、protection, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP Register, a 64-bit Unique Serial Number and three 256-bytes Security Registers. 2. FEATURES New Family of SpiFlash Memories W25Q128F
27、V: 128M-bit / 16M-byte Standard SPI: CLK, /CS, DI, DO, /WP, /Hold Dual SPI: CLK, /CS, IO 0 , IO 1 , /WP, /Hold Quad SPI: CLK, /CS, IO 0 , IO 1 , IO 2 , IO 3 QPI: CLK, /CS, IO 0 , IO 1 , IO 2 , IO 3 Software & Hardware Reset Highest Performance Serial Flash 104MHz Single, Dual/Quad SPI clocks 208/416
28、MHz equivalent Dual/Quad SPI 50MB/S continuous data transfer rate More than 100,000 erase/program cycles More than 20-year data retention Efficient “Continuous Read” and QPI Mode Continuous Read with 8/16/32/64-Byte Wrap As few as 8 clocks to address memory Quad Peripheral Interface (QPI) reduces in
29、struction overhead Allows true XIP (execute in place) operation Outperforms X16 Parallel Flash Low Power, Wide Temperature Range Single 2.7 to 3.6V supply 4mA active current, 1A Power-down (typ.) -40C to +85C operating range Flexible Architecture with 4KB sectors Uniform Sector/Block Erase (4K/32K/6
30、4K-Byte) Program 1 to 256 byte per programmable page Erase/Program Suspend & Resume Advanced Security Features Software and Hardware Write-Protect Power Supply Lock-Down and OTP protection Top/Bottom, Complement array protection Individual Block/Sector array protection 64-Bit Unique ID for each devi
31、ce Discoverable Parameters (SFDP) Register 3X256-Bytes Security Registers with OTP locks Volatile & Non-volatile Status Register Bits Space Efficient Packaging 8-pin SOIC / VSOP 208-mil 8-pin PDIP 300-mil 8-pad WSON 6x5-mm / 8x6-mm 16-pin SOIC 300-mil (additional /RESET pin) 24-ball TFBGA 8x6-mm Con
32、tact Winbond for KGD and other options W25Q128FV Publication Release Date: October 09, 2013 - 6 - Revision I 3. PACKAGE TYPES AND PIN CONFIGURATIONS 3.1 Pin Configuration SOIC / VSOP 208-mil 1 2 3 4 8 7 6 5 /CS DO (IO 1 ) /WP (IO 2 ) GND VCC /HOLD or /RESET (IO 3 ) DI (IO 0 ) CLK Top ViewFigure 1a.
33、W25Q128FV Pin Assignments, 8-pin SOIC / VSOP 208-mil (Package Code S, T) 3.2 Pad Configuration WSON 6x5-mm / 8x6-mm 1 2 3 4 /CS DO (IO 1 ) /WP (IO 2 ) GND VCC /HOLD or /RESET (IO 3 ) DI (IO 0 ) CLK Top View8 7 6 5Figure 1b. W25Q128FV Pad Assignments, 8-pad WSON 6x5-mm / 8x6-mm (Package Code P, E) 3.
34、3 Pin Description SOIC / VSOP 208-mil, WSON 6x5-mm / 8x6-mm PIN NO. PIN NAME I/O FUNCTION 1 /CS I Chip Select Input 2 DO (IO1) I/O Data Output (Data Input Output 1) (1)3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2) (2)4 GND Ground 5 DI (IO0) I/O Data Input (Data Input Output 0) (1)6 CLK
35、I Serial Clock Input 7 /HOLD or /RESET (IO3) I/O Hold or Reset Input (Data Input Output 3) (2)8 VCC Power Supply Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual
36、 SPI. W25Q128FV - 7 - 3.4 Pin Configuration SOIC 300-mil 1 2 3 4 /CS DO (IO 1 ) /WP (IO 2 ) GND VCC /HOLD (IO 3 ) DI (IO 0 ) CLK Top ViewNC /RESET NC NC NC NC NC NC 5 6 7 8 10 9 11 12 13 14 15 16Figure 1c. W25Q128FV Pin Assignments, 16-pin SOIC 300-mil (Package Code F) 3.5 Pin Description SOIC 300-m
37、il PIN NO. PIN NAME I/O FUNCTION 1 /HOLD (IO3) I/O Hold Input (Data Input Output 3) (2)2 VCC Power Supply 3 /RESET I Reset Input (3)4 N/C No Connect 5 N/C No Connect 6 N/C No Connect 7 /CS I Chip Select Input 8 DO (IO1) I/O Data Output (Data Input Output 1) (1)9 /WP (IO2) I/O Write Protect Input (Da
38、ta Input Output 2) (2)10 GND Ground 11 N/C No Connect 12 N/C No Connect 13 N/C No Connect 14 N/C No Connect 15 DI (IO0) I/O Data Input (Data Input Output 0) (1)16 CLK I Serial Clock Input Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 IO3 are used for Quad SPI instructi
39、ons, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI. 3. The /RESET pin on SOIC-16 package is independent of the HOLD/RST bit and QE bit settings in the Status Register. This pin can be treated as No Connect in the system if RESET function is not needed W25Q128FV Publicati
40、on Release Date: October 09, 2013 - 8 - Revision I 3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) D1 /HOLD(IO 3) /RESET DI(IO 0) DO(IO 1) /WP (IO 2) D2 D3 D4 NC E1 NC NC NC E2 E3 E4 NC F1 NC NC NC F2 F3 F4 NC A1 NC NC NC A2 A3 A4 NC B1 VCC GND CLK B2 B3 B4 NC C1 NC /CS C2 C3 C4 NC Top V
41、iew Package Code C D1 /HOLD(IO 3) /RESET DI(IO 0) DO(IO 1) /WP (IO 2) D2 D3 D4 NC E1 NC NC NC E2 E3 E4 NC B5 NC NC NC A2 A3 A4 NC B1 VCC GND CLK B2 B3 B4 NC C1 NC /CS C2 C3 C4 NC Top View Package Code B C5 NC D5 NC E5 NC A5 NCFigure 1d. W25Q128FV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code
42、B & C) 3.7 Ball Description TFBGA 8x6-mm BALL NO. PIN NAME I/O FUNCTION B2 CLK I Serial Clock Input B3 GND Ground B4 VCC Power Supply C2 /CS I Chip Select Input C4 /WP (IO2) I/O Write Protect Input (Data Input Output 2) (2)D2 DO (IO1) I/O Data Output (Data Input Output 1) (1)D3 DI (IO0) I/O Data Inp
43、ut (Data Input Output 0) (1)D4 /HOLD or /RESET (IO3) I/O Hold or Reset Input (Data Input Output 3) (2)Multiple NC No Connect Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for S
44、tandard/Dual SPI. W25Q128FV - 9 - 3.8 Pin Configuration PDIP 300-mil 1 2 3 4 8 7 6 5 /CS DO (IO 1 ) /WP (IO 2 ) GND VCC /HOLD or /RESET(IO 3 ) DI (IO 0 ) CLK Top ViewFigure 1e. W25Q128FV Pin Assignments, 8-pin PDIP (Package Code A) 3.9 Pin Description PDIP 300-mil PIN NO. PIN NAME I/O FUNCTION 1 /CS
45、 I Chip Select Input 2 DO (IO1) I/O Data Output (Data Input Output 1) (1)3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2) (2)4 GND Ground 5 DI (IO0) I/O Data Input (Data Input Output 0) (1)6 CLK I Serial Clock Input 7 /HOLD or /RESET (IO3) I/O Hold or Reset Input (Data Input Output 3) (2)8
46、 VCC Power Supply Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI. W25Q128FV Publication Release Date: October 09, 2013 - 10 - Revision I 4. PIN DESCRIPTION
47、S 4.1 Chip Select (/CS) The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an
48、 internal erase, program or write status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before
49、a new instruction will be accepted. The /CS input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure 58). If needed a pull-up resister on the /CS pin can be used to accomplish this. 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) The W25Q128FV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to
