1、April 2013 AC701 PCIe Design Creation XTP227 Copyright 2013 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: T
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5、GEMENT OF THIRD-PARTY RIGHTS. Revision History Date Version Description 04/03/13 3.0 Regenerated for 2013.1. AR54232 fixed. Added AR55494 and AR55711. 02/04/13 2.1 As per AR54044, added 2012.4 device pack. Added AR53561, AR54232, and AR54223. 12/18/12 2.0 Regenerated for 2012.4. AR52487 fixed. AR526
6、60 fixed. 10/23/12 1.0 Initial Version. Added AR52487. Added AR44635. Added AR52660. Overview Artix-7 PCIe x4 Gen 2 Capability Xilinx AC701 Board Software Requirements AC701 Setup Compile PCIe Cores Generate x4 Gen 2 PCIe Core and MCS File Program AC701 Flash with PCIe Design Running the PCIe x4 Gen
7、 2 Design References IP Release Notes Guide XTP025 Note: This presentation applies to the AC701 Artix-7 PCIe x4 Gen 2 Capability AC701 Supports PCIe Gen 1 and Gen 2 Capability x4, x2, or x1 Gen 1 and Gen 2 lane width See DS821 for details LogiCORE PIO Example Design RDF0225.zip Available through htt
8、p:/ LogiCORE Integrated Block for PCI Express See UG477 for details Note: Presentation applies to the AC701 Artix-7 PCIe x4 Gen 2 Capability Integrated Block for PCI Express PCI Express Base 2.0 Specification Configurable for Endpoint or Root Port Applications AC701 configured for Endpoint Applicati
9、ons GTX Transceivers implement a fully compliant PHY Large range of maximum payload size 128 / 256 / 512 / 1024 bytes Configurable BAR spaces Up to 6 x 32 bit, 3 x 64 bit, or a combination Memory or IO BAR and ID filtering Management and Statistics Interface Note: Presentation applies to the AC701 X
10、ilinx AC701 Board Vivado Software Requirements Xilinx Vivado Design Suite 2013.1, Design Edition Note: Presentation applies to the AC701 PciTree Software Requirement PciTree Bus Viewer Free download HLP.SYS must be copied to C:WINDOWSsystem32drivers directory Note: Presentation applies to the AC701
11、Generate x4 Gen 2 PCIe Core Open Vivado Start All Programs Xilinx Design Tools Vivado 2013.1 Vivado Select Create New Project Note: Presentation applies to the AC701 Generate x4 Gen 2 PCIe Core Click Next Note: Presentation applies to the AC701 Set the Project name and location to ac701_pcie and C:
12、Check Create Project Subdirectory Generate x4 Gen 2 PCIe Core Note: Presentation applies to the AC701 Generate x4 Gen 2 PCIe Core Select RTL Project Select Do not specify sources at this time Note: Presentation applies to the AC701 Generate x4 Gen 2 PCIe Core Select the Family: Artix-7, Package: fbg
13、676, and Speed Grade: -2 Note: Presentation applies to the AC701 Generate x4 Gen 2 PCIe Core Click Finish Note: Presentation applies to the AC701 Generate x4 Gen 2 PCIe Core Click on IP Catalog Note: Presentation applies to the AC701 Generate x4 Gen 2 PCIe Core Select 7 Series Integrated Block for P
14、CI Express, v2.0 under Standard Bus Interfaces Note: Presentation applies to the AC701 Generate x4 Gen 2 PCIe Core Right click on 7 Series PCIe Version 1.8 Select Customize IP Note: Presentation applies to the AC701 Generate x4 Gen 2 PCIe Core Under the Basic tab, set the Component name to ac701_pci
15、e_x4_gen2 Set Board to AC701 Set Silicon to GES and Production Set the lane Width to X4 Set the Link Speed to 5 GT/s Set the Ref Clock to 100 MHz Click on IDs tab Note: Presentation applies to the AC701 Generate x4 Gen 2 PCIe Core Note the ID Initial Values Vendor ID = 10EE Device ID = 7024 Revision
16、 ID = 00 Subsystem Vendor ID = 10EE Subsystem ID = 0007 Click on BARs tab Note: Presentation applies to the AC701 Generate x4 Gen 2 PCIe Core Under the BARs tab, BAR 0 Set to 1 Megabytes Click OK Note: Presentation applies to the AC701 Generate x4 Gen 2 PCIe Core PCIe design appears in Design Source
17、s The PCIe IP is already “checked” but still needs to be generated Note: Presentation applies to the AC701 Compile Example Design Right-click on ac701_pcie_x4_gen2 and select Generate Output Products Note: Presentation applies to the AC701 Compile Example Design Select Examples and click OK Note: Pr
18、esentation applies to the AC701 Compile Example Design Once the Generate step is complete, a check (re)appears on the IP Note: Presentation applies to the AC701 Modify PCIe Core As per AR44635, the design must be modified Open the file: /.srcssources_1ip ac701_pcie_x4_gen2ac701_pcie_x4_gen2example_d
19、esign xilinx_pcie_2_1_ep_7x.v Add this line: input emcclk, Modify PCIe Core As per AR44635, the design must be modified In the XDC file xilinx_pcie_2_1_ep_7x_4_lane_gen2_xc7a200t-fbg676-2_AC701.xdc Add these lines: set_property LOC P16 get_ports emcclk set_property IOSTANDARD LVCMOS33 get_ports emcc
20、lk Modify PCIe Core As per UG470, UG628, and N25Q256 Flash specifications In the XDC file, xilinx_pcie_2_1_ep_7x_4_lane_gen2_xc7a200t-fbg676-2_AC701.xdc, add these lines: set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 current_design set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 current_design s
21、et_property BITSTREAM.GENERAL.COMPRESS TRUE current_design set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES current_design Modify PCIe Core Details on the bitgen command: N25Q256 Maximum Frequency: 108 MHz; AC701 EMCCLK Freq: 90 MHz BITSTREAM.CONFIG.SPI_BUSWIDTH 4: For Quad SPI BITSTREAM.CONFIG.EXTMA
22、STERCCLK_EN div-1: Sets the EMCCLK in the FPGA to divide by 1 BITSTREAM.GENERAL.COMPRESS TRUE: Shrinks the bitstream BITSTREAM.CONFIG.SPI_FALL_EDGE YES: Improves the speed of SPI loading Compile Example Design Right-click on ac701_pcie_x4_gen2 and select Open IP Example Design Compile Example Design A new project is created under /example_project The original project window can be closed Note: Presentation applies to the AC701
