1、Foundation items: Supported by the Natural Science Foundation of Jiangsu Province of China (BK20131072)Biography: CHENG Wei, male, Shandong, China. Ph.D. Research fields focus on InP HBTs and ICs. E-mail: * Corresponding author: E-mail: 0.5m InP DHBT Technology for 100GHz+ Mixed Signal Integrated Ci
2、rcuitsCHENG Wei (程伟)*, ZHANG You-Tao (张有涛), WANG Yuan (王元) , NIU Bin (牛斌), LU Hai-Yan (陆海燕), CHANG Long (常龙), XIE Jun-Ling (谢俊领)Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing, 210016, China.*Corresponding author. Email:
3、Abstract: A high performance 3 inch 0.5m InP double heterojunction bipolar transistor (DHBT) technology with three interconnect layers has been developed. The epitaxial layer structure and geometry parameters of the device were carefully studied to get the needed performance. The 0.55m2 InP DHBTs de
4、monstrated ft =350GHz, fmax=532GHz and BVCEO=4.8V, which were modeled using Agilent-HBT large signal model. Static and dynamic frequency dividers designed and fabricated with this technology have demonstrated maximum clock frequencies of 114GHz and 170GHz, respectively. The ultra high speed 0.5m InP
5、 DHBT technology offers a combination of ultra high speed and high breakdown voltage, which makes it an ideal candidate for next generation 100GHz+ mixed signal integrated circuits.PACS codes:, 85.30.De, 71.55.EqKey words: InP, heterojunction bipolar transistor, frequency divider面向 100GHz+数模混合电路的 0.
6、5m InP DHBT 工艺程伟，张有涛，王元，牛斌，陆海燕，常龙，谢俊领微波毫米波单片集成和模块电路重点实验室，南京电子器件研究所江苏省南京市中山东路 524 号， 210016摘要: 本文报道了一种高性能的 3 英寸磷化铟双异质结双极型晶体管工艺。发射极尺寸为 0.55m2 的磷化铟双异质结双极型晶体管，电流增益截止频率以及最高振荡频率分别达到 350GHz 以及 532GHz，击穿电压 4.8V。基于该工艺研制了 114GHz 静态分频器以及 170GHz 动态分频器两款工艺验证电路，这两款电路的工作频率均处于国内领先水平。关键词: 磷化铟，异质结双极型晶体管，分频器中图分类号: TN3
7、22+.8文献标识码: AIntroductionThe combination of ultra high speed and high breakdown voltage makes InP double heterojunction bipolar transistors (DHBTs) particularly suitable for high speed mixed signal ICs and sub-MMW MMICs (s-MMICs). To date, several outstanding circuits have been demonstrated in InP D
8、HBT technology, including static frequency dividers with an operating frequency above 200GHz 1 and 210GHz power amplifiers with an output power above 200mW 2. For mixed signal ICs, the static frequency divider and dynamic frequency divider are usually used as benchmark circuits for a given device te
9、chnology. Prior to this work, the highest reported clock rates for the static frequency divider and dynamic frequency divider in an InP DHBT technology were both 100GHz in China 3 4 5. In this paper, we report on the development of a 0.5m InP DHBT technology, optimized for the fabrication of 100GHz+
10、 clock mixed signal ICs. The 0.5m InP DHBTs were modeled using Agilent-HBT (AHBT) large signal models. A static frequency divider and a dynamic frequency divider were fabricated with maximum clock frequencies of 114GHz and 170GHz, respectively.Design and FabricationThe InP DHBT structure was grown u
11、sing molecular beam epitaxy (MBE) on a 3-inch semi-insulating InP substrate. The InP DHBT epitaxy structure is given in Tab.1, which consists of a thin highly carbon-doped InGaAs base to reduce the base contact resistivity. A base contact resistivity of 3.9-m2 was extracted from Transmission Line Mo
12、del (TLM) measurement on fabricated InP DHBT wafers. A composite collector including an InGaAs setback layer and an InP pulse doping layer was used to eliminate the conduction band spike at the base-collector interface. The more detailed design and optimization methods of the composite collector cou
13、ld be found in Ref. 6.Tab.1. InP DHBT epitaxial layer structure表 1. InP DHBT 外延层结构Layer Material Thickness (nm) DopantEmitter Contact InGaAs 200 SiEmitter InP 200 SiBase InGaAs 35 CSet-back InGaAs 30 Si- doping InP 20 SiCollector InP 150 SiCollector Contact InGaAs 50 SiSub-collector InP 200 SiEtch-s
14、top InGaAs 10 udInP substrate S. I.According to the scaling laws of bipolar transistors, increasing the InP DHBT bandwidth requires both vertical scaling of the epitaxy layer and lateral scaling of the transistor junction dimensions. For this reason, besides the vertical layer structure optimization
15、, the horizontal geometry scaling was also carefully studied in order to reduce the resistive and capacitive parasitics, which were very important to improve the high frequency performances of the HBTs, such as the maximum current gain cutoff frequency (ft) and maximum power gain cutoff frequency (f
16、max). Fig.1 illustrates key geometry parameters of an InP DHBT, including emitter contact width (WEC), emitter contact length (LEC), base contact width (WBC), base contact length (LBC), emitter mesa undercut (WBE) and collector contact width (WCC). Fig.2 shows the expected fmax versus some key geome
17、try parameters. The geometry parameters of the device were carefully designed and optimized under the guidance of these relationships.(a) (b)Fig.1 Key geometry parameters of an InP DHBT: (a) top view; (b) cross section图 1. InP DHBT 器件特征尺寸：(a) 俯视图 (b)剖面图(a) (b)Fig.2. Simulated fmax versus some key ge
18、ometry parameters: (a) WEC and WBE; (b) WEC and WBC图 2. fmax 随器件特征尺寸变化曲线:(a) WEC and WBE; (b) WEC and WBCThe InP DHBTs were fabricated using a wet-etch triple mesa process. I-line photolithography was used for all photolithographic process steps. Metal posts on base and collector metals were used to
19、 make their heights at the same level as that of emitter contact. Thin film NiCr resistor and SiN MIM capacitor fabricated on the InP substrate were used as passive components. BCB was used for device passivation and planarization. The low permittivity dielectric of BCB was also used as the low-loss
20、 interlayer dielectric between the three level metals. In addition, the second metal or the third metal could also be used as the ground plane to form the inverted microstrip environment. The cross section of the 0.5m InP DHBT technology is shown in Fig.3.Fig.3. Cross-section of the 0.5m InP DHBT te
21、chnology图 3. 0.5m InP DHBT 工艺剖面图The Agilent-HBT model was used for large signal modeling the InP DHBTs. This model takes into account various unique properties of InP DHBTs, such as collector transit time modulation with applied bias, base-collector current blocking at high collector currents. Some
22、key parameters values of the InP DHBT model are summarized in Tab.2. RE is the emitter resistance of the InP DHBT. RCI and RCX are the intrinsic and extrinsic collector resistances, respectively. RBI and RBX are the intrinsic and extrinsic base resistances, respectively. Cje is the base-emitter capa
23、citance and Cjc is the base-collector capacitance. Good agreements between measured and modeled S-parameters were achieved, as shown in Fig.4. The large signal model was then employed in the design of static and dynamic dividers. Tab.2. Key parameters of the InP DHBT model表 2. InP DHBT 模型关键参数Paramet
24、er Value UnitsRE 4.27 OhmRCI 2.03 OhmRCX 0.49 OhmRBI 25.24 OhmRBX 2.40 OhmCje 15.49 fFCjc 36.76 fFFig.4 Modeled (lines) versus measured (cross symbols) S-parameters图 4. 大信号模型仿真与实测结果对比 S 参数A static frequency divider and a dynamic frequency divider were designed as demonstration ICs for the 0.5m InP D
25、HBT technology, which were both highly optimized to obtain peak performances. The dividers were implemented with emitter-coupled-logic (ECL) topology, which could reduce the gate delay compared to the current-model-logic (CML) topology. The emitter followers were inserted between the master and slav
26、e latches in order to implement impedance transformation and provide appropriate bias for the transistor to obtain the best speed performance. Moreover, in order to maximize the speed and bandwidth of the dividers, peaking inductors were added in series with the load resistances to decrease the tran
27、sition time. The input and output of the dividers were all designed to be single-ended interfaces for convenient measurement, and the interface circuitry of the divider core was carefully designed to avoid affecting performance of the divider core. The layout of the divider was a very important phas
28、e during the whole design. A compact layout could reduce the parasitic capacitance and inductance effectively, which would slow down the divider obviously. A dense wiring scheme and a thin film microstrip line environment were used to reduce the interconnect delays and maintain the signal integrity.
29、 Moreover, some key transmission lines were simulated in the ADS momentum to take into account both the transmission line effect and signal integrity. Fig.5 illustrates the simplified schematics of the static and dynamic frequency dividers. The maximum simulated toggle rates for the static and dynam
30、ic dividers were 140GHz and 212GHz, respectively.(a) (b)Fig.5 Simplified schematic of the divider core: (a) static divider; (b) dynamic divider图 5. 分频器核心原理图:(a) 静态分频器 (b)动态分频器Measurement and DiscussionAfter fabrication, measurements for the InP DHBTs were performed at room temperature. The microscop
31、e picture of the InP DHBT is shown in Fig.6, the area of the single emitter finger is 0.55m2 and the base contact width is 0.5m at each side of the emitter. The DC characteristics of the fabricated InP DHBTs were measured using B1500 semiconductor parameter analyzer. Common-emitter current-voltage c
32、haracteristics of an InP DHBT with an emitter area of 0.55m2 are shown in Fig.7. The current gain () is 33 and the common-emitter breakdown voltage (BVCEO) is 4.8V. The offset and the knee voltages are 0.1V and 0.5V, respectively. The small knee voltage and sharp current rising indicate that the cur
33、rent blocking effect has been successfully suppressed by the composite collector 7.Fig.6. Microscope picture of a 0.55m2 DHBT图 6. 0.55m2 DHBT 器件显微镜照片Fig.7. Common-emitter current-voltage characteristics of a 0.55m2 DHBT图 7 发射极面积 0.55m2 DHBT 器件 I-V 特性曲线On-wafer small-signal RF performance was measure
34、d with N5247A vector network analyzer from 0.2 to 67GHz after performing a standard short-open-load-through (SOLT) calibration. On-wafer short and open pad structures identical to those used by the InP DHBTs were measured to deembed the pad parasitics. Fig.8 shows the measured current gain (H21), ma
35、ximum stable/available gain (MSG/MAG) and Masons unilateral Gain (U) as functions of frequency of a 0.55m2 InP DHBT. The small jitter of the measured U was caused by the resonant hole modulation 8. ft and fmax were extracted from the measured H21 and U by using a -20dB/decade slope, respectively, at
36、 a bias condition of VCE=1.5V and IC=11mA. The extrapolated ft and fmax of a 0.55m2 InP DHBT are 350GHz and 532GHz, respectively. Fig.9 shows variation of ft and fmax versus collector current density (Jc) at VCE=1.5V and the Kirk effect is observed at a Jc of 4.8mA/m2 when ft falls to 95% of its pea
37、k value. Table 3 compares recently reported InP DHBTs in China.Fig.8. H21, MSG/MAG and U for a 0.55m2 DHBT versus frequency at VCE=1.5V and IC=11mA图 8. 发射极面积 0.55m2 DHBT 器件 H21, MSG/MAG 以及 U 随频率变化曲线Fig.9. Extrapolated ft and fmax of a 0.55m2 DHBT versus Jc at VCE=1.5V图 9. 发射极面积 0.55m2 DHBT 器件 ft 以及
38、fmax 随电流密度变化曲线Tab.3. Comparison of InP DHBTs 表 3. InP DHBT 性能比较Ref. Technology ft (GHz) fmax (GHz)7 1.6m InP DHBT 242 1069 0.5m InP DHBT - 41610 1.0m InP DHBT 170 256This wok 0.5m InP DHBT 350 532After fabrication, the static and dynamic frequency dividers were measured at room temperature on a wafe
39、r probe station. A conventional 50GHz CW source was used for low frequency measurement. Testing beyond 50GHz in the V, W and D-bands was performed with combination of low frequency source and frequency multiplier modules. The output spectrum of the divider was measured by a 50GHz spectrum analyzer.
40、V-band or W-band harmonic mixer modules were used on the divider output when testing above 100GHz or 150GHz.The maximum clock rates achievable for the static frequency and dynamic frequency dividers were 114GHz and 170GHz, respectively. The maximum simulated toggle rates of the dividers were a littl
41、e higher than those measured from the fabricated circuits, which was probably because only some key but not all of the transmission lines were taken into account during the circuit design process to reduce the time and complexity of the EM simulation. Moreover, the large signal model of the InP DHBT
42、 was implemented based on the measurement data from 200MHz to 67GHz, so there were some errors in the simulation results especially in the frequency range beyond 67GHz. Fig.10 and Fig.11 illustrate the measured output spectrums for the static and dynamic frequency dividers, respectively. Table 4 com
43、pares the performances of recently reported static and dynamic frequency dividers in China. (a) (b)Fig.10. Output spectrums for the static frequency divider: (a) 2GHz input; (b) 114GHz input图 10. 静态分频器输出频谱: (a) 输入频率 2GHz (b)输入频率 114GHz(a) (b)Fig.11. Output spectrums for the dynamic frequency divider
44、: (a) 110GHz input; (b) 170GHz input图 11. 动态分频器输出频谱: (a) 输入频率 110GHz (b)输入频率 170GHzTab.4. Comparison of InP DHBT static and dynamic frequency dividers表 4. InP DHBT 静态和动态分频器性能比较Ref. Type Technology ft / fmax(GHz) Max. operating freq. (GHz) DC power(mW)3 Static 0.7m InP DHBT 280 / 280 83 3504 Dynamic
45、1.0m InP DHBT 214 / 193 83 10605 Static 1.4m InP DHBT 170 / 253 40 650This wok Static 0.5m InP DHBT 350 / 532 114 600This work Dynamic 0.5m InP DHBT 350 / 532 170 550Although ft and fmax could be used to describe the maximum operating frequency the InP DHBT, they are of limited value in predicting t
46、he speed of the high speed mixed-signal ICs. In fact, static and dynamic frequency dividers are usually used as benchmark circuits for a given device technology. The propagation delay of the divider is dependent on the charging times of the parasitic capacitances and resistances encountered in the s
47、ignal path, which could be calculated using the method of open circuit time constants (MOTC). The most significant delay part is CcbVlogic/Ic, where Ccb is the capacitance of the base-collector junction, Vlogic is the logic swing of the circuit, and Ic is the collector current. Therefore, a smaller
48、Ccb and a higher current density are preferred to increase the digital circuit speed. For the current density, as the current density increases, the mobile carriers modify the electric field profile. When the electron concentration in the base-collector depletion region exceeds the doping density of
49、 the collector, the electric field of the collector at the base side will reach zero, the Kirk effect thus occurs and the corresponding collector current density is Kirk current density (JKirk). The Kirk effect causes an additional electron barrier at the base-collector interface, which degrades the DC and RF performances of the InP DHBT, so the operating current density of the InP
