1、盛建伦 ,1,2-17,计算时，可以考虑输出低电平，也可以忽略。,R600,习题参考答案,盛建伦 ,2,2-13,A,B,习题参考答案,盛建伦 ,3,数 字 逻 辑,Digital Logic,青岛理工大学,广义双语教学课程,课程网站 211.64.192.58,盛建伦 ,4,时序逻辑电路,第4章,Sequential logic Circuits,(1),In digital circuits, a flip-flop is a term referring to an electronic circuit that has two stable states and thereby is
2、capable of serving as one bit of memory.,盛建伦 ,5,4.2 触发器 Flip-flops,分类1. 按触发方式（电平触发，脉冲触发，边沿触发）；,功能： 用于记忆1位二进制信号1. 有两个能自行保持的稳定状态，可分别表示0和1；2. 根据不同的输入信号可以置成0或1。,Flip-flops can be either simple (transparent) or clocked.,2. 按逻辑功能（RS, JK, D, T）。,Simple flip-flops can be built around a pair of cross-coupled
3、 inverting elements: vacuum tubes, bipolar transistors, field effect transistors, inverters, and inverting logic gates have all been used in practical circuitsperhaps augmented by some gating mechanism (an enable/disable input).,盛建伦 ,6,RS锁存器 SR latch,4.2.1 基本RS触发器 SR Flip-flop,The fundamental latch
4、is the simple SR flip-flop, where S and R stand for set and reset, respectively. It can be constructed from a pair of cross-coupled NAND or NOR logic gates.,电路结构,Set：置位，置1,Reset：复位，置0,*,RS锁存器 SR latch,保持,现态,次态,SD=1，RD=0置1,RD=1，SD=0置0,SD=RD=0保持,SD=RD=1锁存器为非法状态，,8,保持,现态,次态,1,1,0,0,0,0,1,1,0,0,0,0,1,1,
5、不定,S、R同 时为1,S、R同时 从1变0,进入不定状态,9,*,RS锁存器 SR latch,用与非门构成的RS锁存器,保持,特性表,不定,20:10:03,盛建伦 ,10,动作特点：在任何时刻，输入都能直接改变输出的状态。,例：,RS锁存器 SR latch,4.2.2 同步RS触发器,电路结构与工作原理,电平触发的触发器,1,0,1,1,保持,同步RS锁存器,电平触发的触发器,The name flip-flop was later derived from the sound produced on a speaker connected to one of the back-cou
6、pled amplifiers outputs during the trigger process within the circuit.,S=1，R=0置1,R=1，S=0置0,S=R=0保持,S=R=1触发器为非法状态,盛建伦 ,13,同步(门控)RS触发器,异步置位端,异步复位端,A flip-flop is usually controlled by one or two control signals and/or a gate or clock signal. The output often includes the complement as well as the norm
7、al output. As flip-flops are implemented electronically, they require power and ground connections.,当CLK=0时可将触发器置位/复位,20:10:03,盛建伦 ,14,动作特点： 在CLK=1的全部时间里， S和R的 变化都将引起输出状态的变化。,同步RS触发器,初始状态Q=0,D型锁存器 （同步D触发器）,16,脉冲触发的触发器 pulse-triggered,电路结构与工作原理,4.2.5 主从RS触发器,主触发器master,从触发器slave,CP,Clock Pulse,提高可靠性，
8、要求每个CP 周期输出状态只能改变1次,CP,延迟输出,20:10:03,主触发器,从触发器,主从RS触发器 Masterslave RS flip-flop,It is called masterslave because the second latch in the series only changes in response to a change in the first (master) latch.,波形图,CP,主从RS触发器,主触发器,从触发器,初始状态Q=0,2018年9月2日8时10分,Homework,1、画出下图所示电路输出端Q和 的波形,2、画出下图所示电路输出端Q和 的波形,Homework,3、主从结构的RS触发器各 输入端波形如图所示，画 出输出端Q和 的波形,4、主从结构的RS触发器各 输入端波形如图所示，画 出输出端Q和 的波形,盛建伦 ,21,测验2,请写好自己的姓名、学号、班级,盛建伦 ,22,1、 (30分) 试用74HC138和最少数量的2输入逻辑门设计一个不一致电路。A、B、C 三个输入不一致时，输出为1，三个输入一致时，输出为0。,2、(35分) 用数据选择器产生逻辑函数,3、 (35分) 设计一个代码转换电路，输入为4位二进制代码，输出为4位循环码。,
