1、EDA 10-3 ADC0809 FSM-1123 FSM ADC0809 FSM ADC0809 4 1.ADC0809 ADC0809 8 8 ADC 1.ADC0809 AD0809 0124 3 ADC0809 1.ADC0809采样状态机结构框图PROCESSREG PROCESSCOM PROCESSLATCH1 current_statenext_stateLOCK FSMCLK ADC0809Q7.0 A/D clk=750KHzALESTARTOEADDA EOCD7.02.ADC0809 FPGA/CPLDIN0LIBRARY IEEE;USE IEEE.STD_LOGIC
2、_1164.ALL;ENTITY ADC0809 ISPORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);CLK,EOC:IN STD_LOGIC;-CLK AD0809 EOCLOCK_T:OUT STD_LOGIC;-LOCK ALE,START,OE,ADDA:OUT STD_LOGIC;-AD0809 Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-END AD0809;ARCHITECTURE behav OF AD0809 ISTYPE states IS(st0,st1,st2,st3,st4);SIGNAL current_st
3、ate,next_state:states:=st0;SIGNAL REGL:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL LOCK:STD_LOGIC;BEGIN-0809 0 LOCK_T=LOCK;3.ADC0809 FSM 10-2REG:PROCESS(CLK)-BEGINIF(CLKEVENT AND CLK=1)THEN current_state=next_state;END IF;END PROCESS REG;-current_state LATCH1:PROCESS(LOCK)-BEGINIF LOCK=1 AND LOCKEVENT THEN
4、REGL=D;END IF;END PROCESS;-LOCK Q=REGL;END behav;接上页接上页COM:PROCESS(current_state,EOC)BEGIN-CASE current_state IS WHEN st0=ALE=0;START=0;LOCK=0;OE=0;-0809 next_state ALE=1;START=1;LOCK=0;OE=0;-next_state ALE=0;START=0;LOCK=0;OE=0;next_state=st3;-ELSE next_state ALE=0;START=0;LOCK=0;OE=1;next_state ALE=0;START=0;LOCK=1;OE=1;next_state next_state=st0;END CASE;END PROCESS COM;ALE START LOCK OE EOC 0 0 0 0 1 0_ 1 1 0 0 X 1_ 0 0 0 0 0 2_ 0 0 0 0 1 2_ 0 0 0 1 1 3_ 0 0 1 1 1 4_4.ADC0809 FSMADC0809ADC0809 FSM
