1、 August 2010 Doc ID 17863 Rev 1 1/31PM0075Programming manualSTM32F10xxx Flash memory microcontrollersIntroductionThis programming manual describes how to program the Flash memory of STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx microcontrollers. For convenience, these will be re
2、ferred to as STM32F10xxx in the rest of this document unless otherwise specified.The STM32F10xxx embedded Flash memory can be programmed using in-circuit programming or in-application programming.The in-circuit programming (ICP) method is used to update the entire contents of the Flash memory, using
3、 the JTAG, SWD protocol or the boot loader to load the user application into the microcontroller. ICP offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. In contrast to the ICP method, in-application programming (IAP) can use any communic
4、ation interface supported by the microcontroller (I/Os, USB, CAN, UART, I2C, SPI, etc.) to download programming data into memory. IAP allows the user to re-program the Flash memory while the application is running. Nevertheless, part of the application has to have been previously programmed in the F
5、lash memory using ICP.The Flash interface implements instruction access and data access based on the AHB protocol. It implements a prefetch buffer that speeds up CPU code execution. It also implements the logic necessary to carry out Flash memory operations (Program/Erase). Program/Erase operations
6、can be performed over the whole product voltage range. Read/Write protections and option bytes are also Contents PM00752/31 Doc ID 17863 Rev 1Contents1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.1 Features . . . . . . . . . . . . .
7、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.2 Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Reading/programming the embedded Flash memory . . . . . . . . . . . . . 112.1 Introduction . . . . . . . . . . . .
8、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.2 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.2.1 Instruction fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.2.2
9、 D-Code interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2.3 Flash access controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.3 Flash program and erase controller (FPEC) . . . . . . . . . . . . . . . . . . . . . .
10、122.3.1 Key values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.3.2 Unlocking the Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.3.3 Main Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . .
11、. . . . . 132.3.4 Flash memory erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.3.5 Option byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.4 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12、 . . . . . . . . . . . . . . . 172.4.1 Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.4.2 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.4.3 Option byte block write protection . . .
13、 . . . . . . . . . . . . . . . . . . . . . . . . . . 192.5 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.1 Flash access control register
14、 (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . . . 233.2 FPEC key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243.3 Flash OPTKEY register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . . . 243.4 Flash status register (FLASH_SR) . . . . . . . . . . . .
15、 . . . . . . . . . . . . . . . . . . 253.5 Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.6 Flash address register (FLASH_AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.7 Option byte register (FLASH_OBR) . . . . . . . . . . . . . . .
16、. . . . . . . . . . . . . . 273.8 Write protection register (FLASH_WRPR) . . . . . . . . . . . . . . . . . . . . . . . . 283.9 Flash register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .
17、 . . . . . . . . . . . . . . . . . . 30PM0075 List of tablesDoc ID 17863 Rev 1 3/31List of tablesTable 1. Flash module organization (low-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Table 2. Flash module organization (medium-density devices) . . . . . . . . . .
18、 . . . . . . . . . . . . . . . . . . . 7Table 3. Flash module organization (high-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Table 4. Flash module organization (connectivity line devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Table 5. Flash
19、memory protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Table 6. Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Table 7. Option byte organization. . . . .
20、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Table 8. Description of the option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Table 9. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . .
21、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Table 10. Flash interface - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22、. . . . . . . . . . . . . . . . 30List of figures PM00754/31 Doc ID 17863 Rev 1List of figuresFigure 1. Programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 2. Flash memory Page Erase procedure . . . . . . . . . . . . .
23、. . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 3. Flash memory Mass Erase procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16PM0075Doc ID 17863 Rev 1 5/31GlossaryThis section gives a brief definition of acronyms and abbreviations used in this
24、document: Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kb
25、ytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. The Cortex-M3 core integrates two debug ports: JTAG debug port (JTAG-DP) provides
26、a 5-pin standard interface based on the Joint Test Action Group (JTAG) protocol. SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on the Serial Wire Debug (SWD) protocol.For both the JTAG and SWD protocols please refer to the Cortex M3 Technical Reference Manual Word: data/i
27、nstruction of 32-bit length Half word: data/instruction of 16-bit length Byte: data of 8-bit length FPEC (Flash memory program/erase controller): write operations to the main memory and the information block are managed by an embedded Flash program/erase controller (FPEC). IAP (in-application progra
28、mming): IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running. ICP (in-circuit programming): ICP is the ability to program the Flash memory of a microcontroller using the JTAG protocol, the SWD protocol or the boot loader while the device is mounted
29、 on the user application board. I-Code: this bus connects the Instruction bus of the Cortex-M3 core to the Flash instruction interface. Prefetch is performed on this bus. D-Code: this bus connects the D-Code bus (literal load and debug access) of the Cortex-M3 to the Flash Data Interface. Option byt
30、es: product configuration bits stored in the Flash memory OBL: option byte loader. AHB: advanced high-performance bus.Overview PM00756/31 Doc ID 17863 Rev 11 Overview1.1 Features up to 512 Kbytes of Flash memory Memory organization: Main memory block:4 Kbits 64 bits for low-density devices16 Kbits 6
31、4 bits for medium-density devices64 Kbits 64 bits for high-density devices32 Kbits 64 bits for connectivity line devices Information block:2306 64 bits for connectivity line devices258 64 bits for other devicesFlash memory interface (FLITF) features: Read interface with prefetch buffer (2 64-bit wor
32、ds) Option byte Loader Flash Program / Erase operation Read / Write protection Low-power mode1.2 Flash module organizationThe memory organization is based on a main memory block containing 32 pages of 1 Kbyte (for low-density devices), 128 pages of 1 Kbyte (for medium-density devices), 128 pages of
33、2 Kbyte (for connectivity line devices) or 256 pages of 2 Kbyte (for high-density devices), and an information block as shown in Table 2 and Table 3.PM0075 OverviewDoc ID 17863 Rev 1 7/31Table 1. Flash module organization (low-density devices)Block Name Base addresses Size (bytes)Main memoryPage 0 0
34、x0800 0000 - 0x0800 03FF 1 KbytePage 1 0x0800 0400 - 0x0800 07FF 1 KbytePage 2 0x0800 0800 - 0x0800 0BFF 1 KbytePage 3 0x0800 0C00 - 0x0800 0FFF 1 KbytePage 4 0x0800 1000 - 0x0800 13FF 1 Kbyte.Page 31 0x0800 7C00 - 0x0800 7FFF 1 KbyteInformation blockSystem memory 0x1FFF F000 - 0x1FFF F7FF 2 KbytesO
35、ption Bytes 0x1FFF F800 - 0x1FFF F80F 16Flash memory interface registersFLASH_ACR 0x4002 2000 - 0x4002 2003 4FLASH_KEYR 0x4002 2004 - 0x4002 2007 4FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4FLASH_SR 0x4002 200C - 0x4002 200F 4FLASH_CR 0x4002 2010 - 0x4002 2013 4FLASH_AR 0x4002 2014 - 0x4002 2017 4Rese
36、rved 0x4002 2018 - 0x4002 201B 4FLASH_OBR 0x4002 201C - 0x4002 201F 4FLASH_WRPR 0x4002 2020 - 0x4002 2023 4Table 2. Flash module organization (medium-density devices)Block Name Base addresses Size (bytes)Main memoryPage 0 0x0800 0000 - 0x0800 03FF 1 KbytePage 1 0x0800 0400 - 0x0800 07FF 1 KbytePage
37、2 0x0800 0800 - 0x0800 0BFF 1 KbytePage 3 0x0800 0C00 - 0x0800 0FFF 1 KbytePage 4 0x0800 1000 - 0x0800 13FF 1 Kbyte.Page 127 0x0801 FC00 - 0x0801 FFFF 1 KbyteInformation blockSystem memory 0x1FFF F000 - 0x1FFF F7FF 2 KbytesOption Bytes 0x1FFF F800 - 0x1FFF F80F 16Overview PM00758/31 Doc ID 17863 Rev
38、 1Flash memory interface registersFLASH_ACR 0x4002 2000 - 0x4002 2003 4FLASH_KEYR 0x4002 2004 - 0x4002 2007 4FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4FLASH_SR 0x4002 200C - 0x4002 200F 4FLASH_CR 0x4002 2010 - 0x4002 2013 4FLASH_AR 0x4002 2014 - 0x4002 2017 4Reserved 0x4002 2018 - 0x4002 201B 4FLASH_
39、OBR 0x4002 201C - 0x4002 201F 4FLASH_WRPR 0x4002 2020 - 0x4002 2023 4Table 3. Flash module organization (high-density devices)Block Name Base addresses Size (bytes)Main memoryPage 0 0x0800 0000 - 0x0800 07FF 2 KbytesPage 1 0x0800 0800 - 0x0800 0FFF 2 KbytesPage 2 0x0800 1000 - 0x0800 17FF 2 KbytesPa
40、ge 3 0x0800 1800 - 0x0800 1FFF 2 Kbytes.Page 255 0x0807 F800 - 0x0807 FFFF 2 KbytesInformation blockSystem memory 0x1FFF F000 - 0x1FFF F7FF 2 KbytesOption Bytes 0x1FFF F800 - 0x1FFF F80F 16Flash memory interface registersFLASH_ACR 0x4002 2000 - 0x4002 2003 4FLASH_KEYR 0x4002 2004 - 0x4002 2007 4FLAS
41、H_OPTKEYR 0x4002 2008 - 0x4002 200B 4FLASH_SR 0x4002 200C - 0x4002 200F 4FLASH_CR 0x4002 2010 - 0x4002 2013 4FLASH_AR 0x4002 2014 - 0x4002 2017 4Reserved 0x4002 2018 - 0x4002 201B 4FLASH_OBR 0x4002 201C - 0x4002 201F 4FLASH_WRPR 0x4002 2020 - 0x4002 2023 4Table 2. Flash module organization (medium-d
42、ensity devices) (continued)Block Name Base addresses Size (bytes)PM0075 OverviewDoc ID 17863 Rev 1 9/31The Flash memory is organized as 32-bit wide memory cells that can be used for storing both code and data constants. The Flash module is located at a specific base address in the memory map of each
43、 STM32F10xxx microcontroller type. For the base address, please refer to the related STM32F10xxx reference manual.The information block is divided into two parts: System memory is used to boot the device in System memory boot mode. The area is reserved for use by STMicroelectronics and contains the
44、boot loader which is used to reprogram the Flash memory using the USART1 serial interface. It is programmed by ST when the device is manufactured, and protected against spurious write/erase operations. For further details please refer to AN2606.In connectivity line devices the boot loader can be act
45、ivated through one of the following interfaces: USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in Device mode (DFU: device firmware upgrade). The USART peripheral operates with the internal 8 MHz oscillator (HSI). The CAN and USB OTG FS, however, can only function if an external 8 MHz, 14.
46、7456 MHz or 25 MHz clock (HSE) is present. For further details, please refer to AN2662 (“STM32F105xx and STM32F107xx system memory boot mode”) available from . Option bytesWrite operations to the main memory block and the option bytes are managed by an embedded Flash Program/Erase Controller (FPEC).
47、 The high voltage needed for Program/Erase operations is internally generated.Table 4. Flash module organization (connectivity line devices)Block Name Base addresses Size (bytes)Main memoryPage 0 0x0800 0000 - 0x0800 07FF 2 KbytesPage 1 0x0800 0800 - 0x0800 0FFF 2 KbytesPage 2 0x0800 1000 - 0x0800 1
48、7FF 2 KbytesPage 3 0x0800 1800 - 0x0800 1FFF 2 Kbytes.Page 127 0x0803 F800 - 0x0803 FFFF 2 KbytesInformation blockSystem memory 0x1FFF B000 - 0x1FFF F7FF 18 KbytesOption Bytes 0x1FFF F800 - 0x1FFF F80F 16Flash memory interface registersFLASH_ACR 0x4002 2000 - 0x4002 2003 4FLASH_KEYR 0x4002 2004 - 0x
49、4002 2007 4FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4FLASH_SR 0x4002 200C - 0x4002 200F 4FLASH_CR 0x4002 2010 - 0x4002 2013 4FLASH_AR 0x4002 2014 - 0x4002 2017 4Reserved 0x4002 2018 - 0x4002 201B 4FLASH_OBR 0x4002 201C - 0x4002 201F 4FLASH_WRPR 0x4002 2020 - 0x4002 2023 4Overview PM007510/31 Doc ID 17863 Rev 1The main Flash memory can be protected against different types of unwanted access (read/write/erase). There are two types of protection: Page Write Protection Read ProtectionRefer
