1、Ultra Series 晶体振荡器系列Si547 数据表超低抖动任意四频 XO (80 fs)，0.2 至 1500 MHzSi547 Ultra Series 振荡器系列采用 Silicon Laboratories 先进的第四代DSPLL 技术，提供可选四频的超低抖动和低相位噪声时钟。这款设备经过出厂前预编程，可提供频率范围在 0.2 至 1500 MHz 之间的任意可选四频，分辨率小于 1ppb，可以在整个工作范围内实现整数和小数频率的超低抖动。Si547 振荡器系列提供出色的可靠性、频率稳定性和抗老化性能。片上电源滤波可以实现行业领先的电源噪音抑制特性，简化了使用开关式电源的噪声系统
2、生成低抖动时钟的任务。Si547 振荡器系列采用行业标准 3.25 mm 小型封装，大幅简化供应链，使 Silicon Labs在收到订单后 1-2 周内即可将定制频率样品送达。不同于传统的 XO，Si547 振荡器系列无需使用不同的晶体实现不同的输出频率，而使用单一晶体和基于 DSPLL IC 的方法提供所需输出频率。这一流程也保证了每个设备的 100% 电气测试。Si547 振荡器系列经工厂配置，可以满足各种各样的用户规格，包括频率、输出格式和 OE 引脚位置/极性。特殊配置在发货时经过出厂前编程，消除了与定制频率振荡器有关的长交付周期。主要特点 可以选择 200 kHz 至 1500 M
3、Hz 之间的任意可选四频 超低抖动：80 fs RMS（典型值，12 kHz 20 MHz） 出色的 PSRR 和电源噪声抗扰度：80 dBc（典型值） 比 SAW 振荡器稳定性高 3 倍 相同部件编号可实现 3.3 V、2.5 V 和 1.8V 的供电电压电源操作 提供 LVPECL、LVDS、CML、HCSL、CMOS 和双路 CMOS 输出选项 3.25 mm 封装尺寸 样品交付周期为 1-2 周应用 100G/200G/400G 相干光学 OTN 10G/25G/40G/100G 以太网 3G-SDI/12G-SDI/24G-SDI 广播视频 服务器、开关、存储、网卡、搜索加速 测试和
4、测量 时钟数据恢复 FPGA/ASIC 时钟设计引脚分配123654GNDNC/OEVDDCLK+CLK-OE/NC(Top View)8FS0FS17引脚编号说明1, 2 订购可选选项OE 表示“输出使能”；NC 表示“无连接”3 GND 表示“接地”4 CLK+ 表示“时钟输出”5 CLK- 表示“互补时钟输出”。CMOS 输出格式下不可用。6 VDD 表示“电源电压”7 FS1 表示“频率选择 1”8 FS0 表示“频率选择 0”Phase Error CancellationFixed Frequency CrystalFrequency Flexible DSPLL Low Nois
5、e DriverDigitalLoop FilterDCODigital PhaseDetectorFractionalDividerPhase ErrorOSCPower Supply RegulationNVMBuilt-in Power Supply Noise RejectionControlOE, Frequency Select(Pin Control)Flexible Formats,1.8V 3.3V O | Building a more connected world. Rev. 0.7 1. Ordering GuideThe Si547 XO supports a va
6、riety of options including frequency, output format, and OE pin location/polarity, as shown in the chartbelow. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. SiliconLaboratories provides an online part number configuration uti
7、lity to simplify this process. Refer to to accessthis tool and for further ordering instructions.- - - - - B A G-AAA547 RQuad FrequencyDescriptionXO Series547 20 ppmTemp StabilityA 3.2x5 mmPackageB -40 to 85 CTemperature GradeGDevice RevisionTape and ReelReelRCoil TapeOE PolarityOEPinActive HighPin
8、 1AActive LowPin 1BActive HighPin 2CActive LowPin 2DFrequency Code DescriptionxxxxxxFour unique frequencies can be specified within the supported range of the selected signal format. The frequencies can be arranged in any order from FS1:0=00 to FS1:0=11. A six digit numeric code will be assigned for
9、 the specific combination of frequencies.Order OptionVDD RangeSignal FormatA2.5, 3.3 V LVPECLB1.8, 2.5, 3.3 V LVDSC1.8, 2.5, 3.3 V CMOSD1.8, 2.5, 3.3 V CMLE1.8, 2.5, 3.3 V HCSLF1.8, 2.5, 3.3 V Dual CMOS (In-Phase)G1.8, 2.5, 3.3 V Dual CMOS (Complementary)X1.8, 2.5, 3.3 V Custom1350 ppmTotal Stabilit
10、y2Notes:1.Contact Silicon Labs for non-standard configurations.2.Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 C.3.Create custom part numbers at Technical SupportFrequently Asked Questions (FAQ) Phase Noise Lookup Utility and Relia
11、bility Kits Data SheetOrdering G | Building a more connected world. Rev. 0.7 | 22. Electrical SpecificationsTable 2.1. Electrical SpecificationsVDD = 1.8 V, 2.5 or 3.3 V 5%, TA = 40 to 85 CParameter Symbol Test Condition/Comment Min Typ Max UnitTemperature Range TA 40 85 CFrequency Range FCLK LVPE
12、CL, LVDS, CML 0.2 1500 MHzHCSL 0.2 400 MHzCMOS, Dual CMOS 0.2 250 MHzSupply Voltage VDD 3.3 V 3.135 3.3 3.465 V2.5 V 2.375 2.5 2.625 V1.8 V 1.71 1.8 1.89 VSupply Current IDD LVPECL (output enabled) 107 153 mALVDS/CML (output enabled) 83 121 mAHCSL (output enabled) 86 126 mACMOS (output enabled) 87 1
13、27 mADual CMOS (output enabled) 92 141 mATristate Hi-Z (output disabled) 73 112 mATemperature Stability Frequency stability Grade A 20 20 ppmTotal Stability1 FSTAB Frequency stability Grade A 50 50 ppmRise/Fall Time(20% to 80% VPP)TR/TF LVPECL/LVDS/CML 350 psCMOS / Dual CMOS(CL = 5 pF) 0.5 1.5 nsHCS
14、L, FCLK 50 MHz 450 psDuty Cycle DC All formats 45 55 %Output Enable (OE)Frequency Select (FS0, FS1)2VIH 0.7 VDD VVIL 0.3 VDD VTD Output Disable Time, FCLK 10 MHz 3 sTE Output Enable Time, FCLK 10 MHz 20 sTFS Settling Time after FS Change 10 msPowerup Time tOSC Time from 0.9 VDD until output fre-quen
15、cy (FCLK) within spec 10 msLVPECL Output Option3 VOC Mid-level VDD 1.42 VDD 1.25 VVO Swing (diff) 1.1 1.9 VPPLVDS Output Option4 VOC Mid-level (2.5 V, 3.3 V VDD) 1.125 1.20 1.275 VMid-level (1.8 V VDD) 0.8 0.9 1.0 VVO Swing (diff) 0.5 0.7 0.9 VPPSi547 Data SheetElectrical S | Building a more connect
16、ed world. Rev. 0.7 | 3Parameter Symbol Test Condition/Comment Min Typ Max UnitHCSL Output Option5 VOH Output voltage high 660 750 850 mVVOL Output voltage low 150 0 150 mVVC Crossing voltage 250 350 550 mVCML Output Option (AC-Coupled) VO Swing (diff) 0.6 0.8 1.0 VPPCMOS Output Option VOH IOH = 8/6/
17、4 mA for 3.3/2.5/1.8 V VDD 0.85 VDD VVOL IOL = 8/6/4 mA for 3.3/2.5/1.8 V VDD 0.15 VDD VNotes:1.Total Stability includes 20 ppm temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 C.2.OE includes a 50 k pull-up to VDD for OE active high. Includes a 50 k p
18、ull-down to GND for OE active low. FS0 and FS1 pinseach include a 50 k pull-up to VDD. NC (No Connect) pins include a 50 k pull-down to GND.3.50 to VDD 2.0 V.4.Rterm = 100 (differential).5.50 to GND.Table 2.2. Clock Output Phase Jitter and PSRRVDD = 1.8 V, 2.5 or 3.3 V 5%, TA = 40 to 85 CParameter S
19、ymbol Test Condition/Comment Min Typ Max UnitPhase Jitter (RMS, 12kHz - 20MHz)1All Differential FormatsJ FCLK 200 MHz 80 110 fs100 MHz FCLK 700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase NoiseLookup Tool at 2.1. Phase
20、Jitter vs. Output FrequencySi547 Data SheetElectrical S | Building a more connected world. Rev. 0.7 | 5Table 2.4. Environmental Compliance and Package InformationParameter Test ConditionMechanical Shock MIL-STD-883, Method 2002Mechanical Vibration MIL-STD-883, Method 2007Solderability MIL-STD-883, M
21、ethod 2003Gross and Fine Leak MIL-STD-883, Method 1014Resistance to Solder Heat MIL-STD-883, Method 2036Moisture Sensitivity Level (MSL) 1Contact Pads Gold over NickelNote:1.For additional product information not listed in the data sheet (e.g. RoHS Certifications, MDDS data, qualification data, REAC
22、HDeclarations, ECCN codes, etc.), refer to our “Corporate Request For Information“ portal found here: 2.5. Thermal ConditionsPackage Parameter Symbol Test Condition Value Unit3.25 mm6-pin CLCCThermal Resistance Junction to Ambient JA Still Air, 85 C 79.1 C/WThermal Resistance Junction to Board JB S
23、till Air, 85 C 49.6 C/WMax Junction Temperature TJ Still Air, 85 C 125 CTable 2.6. Absolute Maximum Ratings1Parameter Symbol Rating UnitMaximum Operating Temp. TAMAX 95 CStorage Temperature TS 55 to 125 CSupply Voltage VDD 0.5 to 3.8 CInput Voltage VIN 0.5 to VDD + 0.3 VESD HBM (JESD22-A114) HBM 2.0
24、 kVSolder Temperature2 TPEAK 260 CSolder Time at TPEAK2 TP 2040 secNotes:1.Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specificationcompliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods
25、may affect devicereliability.2.The device is compliant with JEDEC J-STD-020.Si547 Data SheetElectrical S | Building a more connected world. Rev. 0.7 | 63. Dual CMOS BufferDual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. Th
26、isfeature enables replacement of multiple XOs with a single Si547 device.Complementary OutputsIn-Phase OutputsFigure 3.1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase OutputsSi547 Data SheetDual CMOS B | Building a more connected world. Rev. 0.7 | 74. Recommended Output Terminations
27、The output drivers support both AC-coupled and DC-coupled terminations as shown in figures below.CLK-LVPECLReceiver(3.3V, 2.5V)VDDSi54x50 CLK+ 50 Rp RpVDDR1 R1R2 R2CLK-LVPECLReceiver(3.3V, 2.5V)VDDSi54x50 CLK+ 50 VDDR1 R1R2 R2AC-Coupled LVPECL Thevenin Termination DC-Coupled LVPECL Thevenin Terminat
28、ionCLK-LVPECLReceiver50 CLK+ 50 Rp Rp50 R1R2 50 VDD VTTSi54x(3.3V, 2.5V)VDDCLK-LVPECLReceiver50 CLK+ 50 50 R1R2 50 VDD VTTSi54x(3.3V, 2.5V)VDDAC-Coupled LVPECL - 50 w/VTT Bias DC-Coupled LVPECL - 50 w/VTT BiasFigure 4.1. LVPECL Output TerminationsAC Coupled LVPECLTermination Resistor ValuesVDD R1 R2
29、 Rp3.3 V 127 82.5 130 2.5 V 250 62.5 90 DC Coupled LVPECLTermination Resistor ValuesVDD R1 R23.3 V 127 82.5 2.5 V 250 62.5 Si547 Data SheetRecommended Output T | Building a more connected world. Rev. 0.7 | 8DC-Coupled LVDS Source Terminated HCSLAC-Coupled LVDS Destination Terminated HCSLCLK-LVDSRece
30、iver50 CLK+ 50 100 Si54x(3.3V, 2.5V, 1.8V)VDDCLK-LVDSReceiver50 CLK+ 50 100 Si54x(3.3V, 2.5V, 1.8V)VDDCLK-HCSLReceiver50 CLK+ 50 Si54x(3.3V, 2.5V, 1.8V)VDD33 33 50 50 CLK-HCSLReceiver50 CLK+ 50 Si54x(3.3V, 2.5V, 1.8V)VDD50 50 Figure 4.2. LVDS and HCSL Output TerminationsCML Termination without VCM S
31、ingle CMOS TerminationCML Termination with VCM Dual CMOS TerminationCLK-CMLReceiver50 CLK+ 50 100 Si54x(3.3V, 2.5V, 1.8V)VDD50 50 VCMCLK-CMLReceiver50 CLK+ 50 Si54x(3.3V, 2.5V, 1.8V)VDD50 10 CLKNC CMOS Receiver(3.3V, 2.5V, 1.8V)VDDSi54x50 10 CLK+(3.3V, 2.5V, 1.8V)VDDSi54x50 10 CLK-CMOS ReceiversFigu
32、re 4.3. CML and CMOS Output TerminationsSi547 Data SheetRecommended Output T | Building a more connected world. Rev. 0.7 | 95. Package OutlineThe figure below illustrates the package details for the 3.2 5 mm Si547. The table below lists the values for the dimensions shown inthe illustration.Figure 5
33、.1. Si547 Outline DiagramTable 5.1. Package Diagram Dimensions (mm)Dimension Min Nom MaxA 1.02 1.17 1.28A1 0.99 1.10 1.21A2 0.25 0.35 0.55b 0.54 0.64 0.74b1 0.35 0.45 0.55D 5.00 BSCD1 4.65 BSCe 1.27 BSCe1 1.46 BSCE 3.20 BSCE1 2.85 BSCM 0.30 BSCL 0.8 0.9 1.0L1 0.55 0.65 0.75L2 0.05 0.10 0.15Notes:1.A
34、ll dimensions shown are in millimeters (mm) unless otherwise noted.2.Dimensioning and Tolerancing per ANSI Y14.5M-1994.Si547 Data SheetPackage O | Building a more connected world. Rev. 0.7 | 106. PCB Land PatternThe figure below illustrates the 3.2 5.0 mm PCB land pattern for the Si547. The table be
35、low lists the values for the dimensions shownin the illustration.Figure 6.1. Si547 PCB Land PatternTable 6.1. PCB Land Pattern Dimensions (mm)Dimension (mm)C1 2.70E 1.27E1 4.30X1 0.74X2 0.90Y1 1.60Y2 0.70Notes:General1.All dimensions shown are in millimeters (mm) unless otherwise noted.2.Dimensionin
36、g and Tolerancing is per the ANSI Y14.5M-1994 specification.3.This Land Pattern Design is based on the IPC-7351 guidelines.4.All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on aFabrication Allowance of 0.05 mm.Solder Mask Design1.All m
37、etal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 mminimum, all the way around the pad.Stencil Design1.A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release
38、.2.The stencil thickness should be 0.125 mm (5 mils).3.The ratio of stencil aperture to land pad size should be 1:1.Card Assembly1.A No-Clean, Type-3 solder paste is recommended.2.The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.Si547 Data S
39、heetPCB Land P | Building a more connected world. Rev. 0.7 | 117. Top MarkingThe figure below illustrates the mark specification for the Si547. The table below lists the line information.Figure 7.1. Mark SpecificationTable 7.1. Si547 Top Mark DescriptionLine Position Description1 18 “Si547“, xxx = O
40、rdering Option 1, Option 2, Option 3 (e.g. Si547AAA)2 16 Frequency Code(6-digit custom code as described in the Ordering Guide)3 Trace CodePosition 1 Pin 1 orientation mark (dot)Position 2 Product Revision (A)Position 35 Tiny Trace Code (3 alphanumeric characters per assembly release instructions)Po
41、sition 67 Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17)Position 89 Calendar Work Week number (153), to be assigned by assembly siteSi547 Data SheetTop M | Building a more connected world. Rev. 0.7 | 128. Revision History8.1 Revision 0.7 June 27, 2017 Initial release.Si547 Data SheetRevision H | Building a more connected world. Rev. 0.7 | 13http:/Silicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701USAClockBuilder ProOne-click access to Timing tools, documentation, software, source code libraries & m
