1、2012 11 Altera WP-01188-1.0 2012 Altera ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS STRATIX Altera Altera Altera Altera Altera Altera Altera 101 Innovation Drive San Jose, CA 95134 ISO 9001:2008 Registered Altera Cyclone V FPGA Memory FPGA Fabric Hard Memory Controller Hard PHY I/O Cus
2、tom-Configured Avalon-MM Interfaces AFI Interface PHY Calibration Soft Logic 2 Multiport Front-end(MPFE) 2012 11 Altera Altera Cyclone V FPGA Memory Multiport Front-end(MPFE) FPGA Core Logic Multiport Logic Memory Controller PHY Memory Hard Memory Controller FPGA Avalon-MM Interface AFIMultiport Fro
3、nt-end(MPFE) 3 2012 11 Altera Altera Cyclone V FPGA Memory Port 0 Transactions Port 1 Transactions Port 5 Transactions Multiport Scheduling DRAM Burst Scheduling DRAM Burst 1 DRAM Burst 2 DRAM Burst 3 DRAM Burst 8 DRAM Burst Command 4 Multiport Front-end(MPFE) 2012 11 Altera Altera Cyclone V FPGA Me
4、mory Bank 3A Bank 3B Bank 4A User Agent 2 User Agent 1 Hard Memory Controller Bank 7A Bank 8A Hard Memory Controller Multiport Front End Bank 3A Bank 3B Bank 4A User Agent 2 User Agent 1 Hard Memory Controller Bank 7A Bank 8A 5 2012 11 Altera Altera Cyclone V FPGA Memory Bandwidth Data Width (bits)
5、Data Rate Efficiency = Bandwidth 32 bits 2 Clock Edges 400 MHz 70% 17.92 Gbps = Efficiency Number of Clock Cycles That DQ Bus Is Occupied Number of Clock Cycles in the Period - - = (1) t RC Command Address WR B0R0 WR B0R1 WR B0R0 WR B0R1 t RC t RC t RC Command Address WR B0R0 WR B0R1 WR B0R0 WR B0R1
6、 t RC Data Re-Ordering On Data Re-Ordering Off 6 PHY 2012 11 Altera Altera Cyclone V FPGA Memory PHY ACT READ PCH ACT READ PCH ACT READ ACT READ PCH ACT READ PCH ACT READ No Look Ahead With Look Ahead Bank Management Not Efficient Using Idle Cycles for Bank Management Idle Command Bus Not Efficient
7、Read Bank 0 Activate Required Read Bank 1 Pre-Charge Required Read Bank 2 Pre-Charge Required 7 2012 11 Altera Altera Cyclone V FPGA Memory Relative Efficiency Alternating R/W Turnaround and Random Address 50% R/W Turnaround and 50% Random Addresses 0% R/W Turnaround and 100% Random Addresses 1.4 1.2 1 0.8 0.6 0.4 0.2 0 28% More Efficient 17% More Efficient 14% More Efficient Altera Nearest Competitor 8 2012 11 Altera Altera Cyclone V FPGA Memory 2012 11 1.0
