1、DRV8823-Q ZHCS988B JUNE 2012REVISED JANUARY 20134桥桥接接串串行行接接口口电电机机驱驱动动器器查查询询样样品品: DRV8823-Q11特特性性 8V至至32V运运行行电电源源电电压压范范围围针针对对栅栅极极驱驱动动的的内内部部电电荷荷泵泵2符符合合汽汽车车应应用用要要求求内内置置3.3V基基准准电电压压具具有有符符合合AEC-Q100的的下下列列结结果果：串串行行数数字字控控制制接接口口器器件件温温度度1级级：-40C至至125C的的环环境境运运行行温温度度范范围围对对于于欠欠压压、过过热热、和和过过流流情情况况的的完完全全保保护护器器件件人人
2、体体模模型型(HBM)静静电电放放电电(ESD)分分类类等等级级耐耐热热增增强强型型表表面面贴贴装装封封装装H2应应用用范范围围器器件件充充电电器器件件模模型型(CDM) ESD分分类类等等级级C4B具具有有4个个H桥桥的的脉脉宽宽调调制制(PWM)电电机机驱驱动动器器车车载载应应用用驱驱动动两两个个步步进进式式电电机机、一一个个步步进进式式和和两两个个直直流流(DC)电电机机、或或者者四四个个DC电电机机每每绕绕组组电电流流高高达达1.5A低低导导通通电电阻阻可可编编程程最最大大绕绕组组电电流流 3位位绕绕组组电电流流控控制制支支持持多多达达8个个电电流流级级别别可可选选缓缓慢慢或或者者混混
3、合合衰衰减减模模式式说说明明DRV8823-Q1器件为打印机和其它办公自动化设备应用提供了一个集成的电机驱动器解决方案。此电机驱动器电路包含四个H桥驱动器。每个电机驱动器块采用配置为一个H桥的功率MOSFET来驱动电机绕组。一个简单的串行接口只借助几个数字信号即可实现对电机驱动器所有功能的控制。还提供了一个低功耗睡眠功能。此电机驱动器提供PWM电流控制功能。根据一个外部提供的基准电压并借助一个外部电流感测电阻器，可对此电流进行编程。此外，8个电流级别（通过串行接口设定）可实现双极步进式电机的微步进。还提供用于过流保护、短路保护、欠压闭锁和过热保护的内部关断功能。DRV8823-Q1采用48引脚
4、散热薄型小外形尺寸(HTSSOP)封装（环境友好型：符合RoHS标准并且无Sb/Br）。订订购购信信息息(1)TA封封装装(2)可可订订购购部部件件号号正正面面标标记记-40C至125C PowerPAD (HTSSOP)-DCA 2000卷带DRV8823QDCARQ1 DRV8823Q(1)要获得最新的封装和订购信息，请参阅本文档末尾的封装选项附录，或者浏览TI网站。(2)封装图样、热数据和符号可从网站 be aware that an important notice concerning availability, standard warranty, and use in criti
5、cal applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.2PowerPAD is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date. Copyright 20122013, Texas Instruments IncorporatedProducts conform to
6、 specifications per the terms of the TexasInstruments standard warranty. Production processing does not English Data Sheet: SLVSBH2necessarily include testing of all parameters.ChargePump andGate DriveRegulatorThermalShutdownAOUT1AOUT2BOUT1BOUT2GNDABVREF0.1 F16 V0.01F35 V24 V24 V24 V24 V24 VVMCP1CP2
7、VCPAISENBISENVCPOCPVMOscillatorCOUT1COUT2DOUT1DOUT2StepMotorStepMotorVMCISENDISENVMUVLORESETVGDSDATASCLKSCSSSTBRESETnSLEEPnDig.VCCV3P3 3.3 VRegulator0.47 F6.3 VCDVREFSerialInterfaceandLogicPWM H-BridgeDriver APWM H-BridgeDriver BPWM H-BridgeDriver CPWM H-BridgeDriver DDRV8823-Q1ZHCS988BJUNE 2012REVI
8、SED JANUARY 2013 FUNCTIONAL BLOCK DIAGRAMThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle p
9、erformance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.2 Copyright 20122013, Texas Instruments IncorporatedTo LogicESDInternalPulldownHyste
10、resisDRV8823-Q ZHCS988B JUNE 2012REVISED JANUARY 2013PIN FUNCTIONSPIN I/O(1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONSNAME NO.POWER AND GROUNDVM 1, 2, Connect all VM pins together to motor supply voltage.- Motor supply voltage (multiple pins)(4 pins) 23, 24 Bypass to GND with several 0.1-F, 35-
11、V ceramic capacitors.V3P3 16 - 3.3 V regulator output Bypass to GND with 0.47-F, 6.3-V ceramic capacitor.1015, Connect all PGND pins to GND and solder to copper heatsinkGND - Power ground (multiple pins)3439 areas.CP1 7 IO Charge pump flying capacitor Connect a 0.01-F capacitor between CP1 and CP2.C
12、P2 8 IOVCP 9 IO Charge pump storage capacitor Connect a 0.1-F, 16 V ceramic capacitor to VM.MOTOR DRIVERSABVREF 17 I Bridge A 71% 100% 5 5currentICHOP Chopping current accuracy %xVREF = 2.5 V, derived from V3P3; 20% 56% current 10 10(1) Factory option 100 kHz.(2) Factory options for 2.5 s, 5 s or 6.
13、25 s.6 Copyright 20122013, Texas Instruments IncorporatedSCLKSDATASCS574632DataInvalid1DRV8823-Q ZHCS988B JUNE 2012REVISED JANUARY 2013TIMING REQUIREMENTSover operating free-air temperature range (unless otherwise noted)MIN MAX UNIT1 tCYC Clock cycle time 62 ns2 tCLKH Clock high time 25 ns3 tCLKL Cl
14、ock low time 25 ns4 tSU(SDATA) Setup time, SDATA to SCLK 5 ns5 tH(DATA) Hold time, SDATA to SCLK 1 ns6 tSU(SCS) Setup time, SCS to SCLK 5 ns7 tH(SCS) Hold time, SCS to SCLK 1 nsCopyright 20122013, Texas Instruments Incorporated 7AOUT1BOUT1AOUT2BOUT2VMVMISENAISENBAPHASEPre-drivePre-driveVCP, VGDVCP,
15、VGDVMVM+PWMPWMABVREFOCPOCPOCPOCPABDECAYBENBLDACDACAA=55AI2:0BI2:03AENBLBPHASEAI2:033From Serial InterfaceStepMotorDRV8823-Q1ZHCS988BJUNE 2012REVISED JANUARY 2013 FUNCTIONAL DESCRIPTIONPWM Motor DriversThe DRV8823-Q1 device contains four H-bridge motor drivers with current-control PWM circuitry. A bl
16、ockdiagram showing drivers A and B of the motor control circuitry (as typically used to drive a bipolar stepper motor)is shown in Figure 2. Drivers C and D are the same as A and B (though the RDS(ON) of the output FETs isdifferent).Figure 2. Block DiagramNote that there are multiple VM motor power s
17、upply pins. All VM pins must be connected together to the motorsupply voltage.8 Copyright 20122013, Texas Instruments IncorporatedREFXCHOPISENSEVI5 Rc61 c180DRV8823-Q ZHCS988B JUNE 2012REVISED JANUARY 2013Bridge ControlThe xENBL bits in the serial interface registers enable current flow in each H-br
18、idge when set to 1.The xPHASE bits in the serial interface registers control the direction of current flow through each H-bridge. Thefollowing table shows the logic:xPHASE xOUT1 xOUT21 H L0 L HCurrent RegulationThe motor driver employs fixed-frequency PWM current regulation (also called current chop
19、ping). When awinding is activated, the current through it rises until it reaches a threshold, then the current is switched off untilthe next PWM period.The PWM frequency is fixed at 50 kHz, but it may also be set to 100 kHz through the factory option.The PWM chopping current is set by a comparator w
20、hich compares the voltage across a current sense resistorconnected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is inputfrom the VREF pin.The full-scale (100%) chopping current is calculated as follows:(1)Example:If a 0.5- sense resistor is used and
21、 the VREFx pin is 2.5 V, the full-scale (100%) chopping current is:2.5 V/(5 0.5 ) = 1 A.Three serial interface register bits per H-bridge (xI2, xI1 and xI0) are used to scale the current in each bridge asa percentage of the full-scale current set by the VREF input pin and sense resistance. The funct
22、ion of the bits isshown below:Relative CurrentxI2 xI1 xI0(% full-scale chopping current)0 0 0 200 0 1 380 1 0 560 1 1 711 0 0 831 0 1 921 1 0 981 1 1 100Blanking TimeAfter the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of timebefore enabling the cur
23、rent sense circuitry. This blanking time is fixed at 3.75 s. Note that the blanking time alsosets the minimum on time of the PWM.Copyright 20122013, Texas Instruments Incorporated 9xOUT1 xOUT23123Drive currentSlow decay (brake)Fast decay (reverse)VM12DRV8823-Q1ZHCS988BJUNE 2012REVISED JANUARY 2013 D
24、ecay ModeDuring PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM currentchopping threshold is reached. This is shown in Figure 3 as case 1. The current flow direction shown indicatespositive current flow in the step table below.Once the chopping current
25、threshold is reached, the H-bridge can operate in two different states, fast decay orslow decay.In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state toallow winding current to flow in a reverse direction. As the winding current approaches zero, the br
26、idge isdisabled to prevent any reverse current flow. Fast decay mode is shown in Figure 3 as case 2.In slow decay mode, winding current is recirculated by enabling both of the low-side FETs in the bridge. This isshown in Figure 3 as case 3.Figure 3. Decay ModeThe DRV8823-Q1 device supports slow deca
27、y and a mixed decay mode. Mixed decay mode begins as fastdecay, but at a fixed period of time (75% of the PWM cycle) switches to slow decay mode for the remainder ofthe fixed PWM period.Slow or mixed decay mode is selected by the state of the xDECAY bits in the serial interface registers. If thexDEC
28、AY bit is 0, slow decay is selected. If the xDECAY bit is 1, mixed decay is selected.10 Copyright 20122013, Texas Instruments IncorporatedDRV8823-Q ZHCS988B JUNE 2012REVISED JANUARY 2013Protection CircuitsThe DRV8823-Q1 device is fully protected against undervoltage, overcurrent and overtemperature
29、events.Overcurrent Protection (OCP)All of the drivers in the DRV8823-Q1 device are protected with an overcurrent protection (OCP) circuit.The OCP circuit includes an analog current limit circuit, which acts by removing the gate drive form each outputFET if the current through it exceeds a preset lev
30、el. This circuit limits the current to a level that is safe to preventdamage to the FET.A digital circuit monitors the analog current limit circuits. If any analog current limit condition exists for longer thana preset period, all drivers in the device are disabled.The device is re-enabled upon the
31、removal and re-application of power at the VM pins.Thermal Shutdown (TSD)If the die temperature exceeds safe limits, all drivers in the device are shut down.The device remains disabled until the die temperature falls to a safe level. After the temperature falls, the devicemay be re-enabled upon the
32、removal and re-application of power at the VM pin.Undervoltage Lockout (UVLO)If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in thedevice is disabled. Operation resumes when VM rises above the UVLO threshold. The indexer logic is reset
33、to itsinitial condition in the event of an undervoltage lockout.Shoot-Through Current PreventionThe gate drive to each FET in the H-bridge is controlled to prevent any cross-conduction (shoot-through current)during transitions.Serial Data TransmissionData transfers consist of 16 bits of serial data,
34、 shifted into the SDATA pin LSB first.On serial writes to the DRV8823-Q1 device, additional clock edges following the final data bit continues to shiftdata bits into the data register; therefore, the last 16 bits presented are latched and used.One of two registers is selected by setting bits in an a
35、ddress field in the four upper bits in the serial datatransferred (ADDR in the tables below). One 16-bit register is used to control motor number 1 (bridges A and B),and a second 16-bit register is used to control motor 2 (bridges C and D).Data can only be transferred into the serial interface if th
36、e SCS input pin is active high.Data is initially clocked in to a temporary holding register. This data is latched into the motor driver on the risingedge of the SSTB pin. If the SSTB pin is tied high at all times, the data will be latched in after all 16 bits havebeen transferred.Copyright 20122013,
37、 Texas Instruments Incorporated 11SCSSCLKSDATASSTBD0 D8D2 D10D4 D12D6 D14D1 D9D3 D11D5 D13D7See Note 1See Note 2D15DRV8823-Q1ZHCS988BJUNE 2012REVISED JANUARY 2013 Data FormatTable 1. Motor 1 Command (Bridges A and B)D15Bit D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D12ADDRName BDECAY B12 B11 B10 BPHASE BE
38、NBL ADECAY A12 A11 A10 APHASE AENBL(= 0000)Reset x 0 0 0 0 0 0 0 0 0 0 0 0ValueTable 2. Motor 2 Command (Bridges C and D)D15Bit D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D12ADDRName DDECAY D12 D11 D10 DPHASE DENBL CDECAY C12 C11 C10 CPHASE CENBL(= 0001)Reset x 0 0 0 0 0 0 0 0 0 0 0 0ValueSerial Data Timi
39、ngNote 1: Any amount of time is allowed between clocks, or groups of clocks, as long as SCS stays active. This allows8- or 16-bit transfers.Note 2: If more than 16 clock edges are presented while transferring data (while SCS is still high), data continues tobe shifted into the data register.Figure 4
40、. Serial Data Timing Diagram12 Copyright 20122013, Texas Instruments Incorporated2TOT DS(ON) OUT(RMS)P = 4 x R x (I )DRV8823-Q ZHCS988B JUNE 2012REVISED JANUARY 2013THERMAL INFORMATIONThermal ProtectionThe DRV8823-Q1 device has thermal shutdown (TSD) as described above. If the die temperature exceed
41、sapproximately 150C, the device is disabled until the temperature drops to a safe level.Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation,insufficient heatsinking, or too high an ambient temperature.Power DissipationPower dissipation in the D
42、RV8823-Q1 device is dominated by the power dissipated in the output FET resistance,or RDS(ON). Average power dissipation when running a stepper motor can be roughly estimated by Equation 2.(2)Where: PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS
43、outputcurrent applied to each winding. IOUT(RMS) is equal to approximately 0.7x the full-scale output current setting. Thefactor of 4 is derived from the two motor windings, and at any instant two FETs are conducting winding currentfor each winding (one high-side and one low-side). The DRV8823-Q1 de
44、vice has two stepper motor drivers, sothe power dissipation of each must be added together to determine the total device power dissipation.The maximum amount of power that can be dissipated in the DRV8823-Q1 device is dependent on ambienttemperature and heatsinking. The thermal dissipation ratings t
45、able in the datasheet can be used to estimate thetemperature rise for typical PCB constructions.Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This mustbe taken into consideration when sizing the heatsink.HeatsinkingThe PowerPAD integrated circ
46、uit package uses an exposed pad to remove heat from the device. For properoperation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCBwith a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to theground plane
47、. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipateheat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer theheat between top and bottom layers.For details about how to design the PCB, refer to TI
48、application report SLMA002, PowerPAD ThermallyEnhanced Package and TI application brief SLMA004, PowerPAD Made Easy, available at .In general, the more copper area that can be provided, the more power can be dissipated. Figure 5 showsthermal resistance versus copper plane area for both a single-sided PCB with 2-oz copper heatsink area, and a4-layer PCB with 1-oz copper and a solid ground plane. Both PCBs are 76 mm x 114 mm, and 1.6 mm thick. Theheatsink effectiveness increases rapidly to about 20 cm2, then levels off somewhat for larger areas.Six pins on the center of each side of the packa
