1、ProductFolderOrderNowTechnicalDocumentsTools O = output; I/O = bidirectional(2) I/O Type: Digital I/O cells. HY = input hysteresis, current = typical output current4.1.1 Pin Attributes (VQFN-MR Package)Table 4-1 describes the pin attributes for the VQFN-MR package.SPACERTable 4-1. Pin Attributes (VQ
2、FN-MR Package)NAME NO. PULL ATRESET DEF.DIR.(1) I/OType(2) DESCRIPTIONI/O SignalsAUD_CLK B32 PD I/O HY, 4mA PCM clock Fail-safeAUD_FSYNC A35 PD I/O 4 mA PCM frame-sync signal Fail-safeAUD_IN B34 PD I 4 mA PCM data input Fail-safeAUD_OUT B33 PD O 4 mA PCM data output Fail-safeHCI_CTS A29 PU I 8 mAHCI
3、 UART clear-to-sendThe device is allowed to send datawhen HCI_CTS is low.HCI_RX A26 PU I 8 mAHCI universal asynchronousreceiver/transmitter (UART) datareceiveHCI_RTS A32 PU O 8 mAHCI UART request-to-sendThe host is allowed to send data whenHCI_RTS is low.HCI_TX A33 PU O 8 mA HCI UART data transmitTX
4、_DBG B24 PU O 2 mATI internal debug messages. TIrecommends leaving an internal testpoint.Clock SignalsSLOW_CLK A25 I 32.768-kHz clock in Fail-safeXTALP/FREFP B4 I Fast clock in analog (sine wave)Output terminal of fast-clock crystal Fail-safeXTALM/FREFM A4 I Fast clock in digital (square wave)Input
5、terminal of fast-clock crystal Fail-safeAnalog SignalsBT_RF B8 I/O Bluetooth RF I/OnSHUTD A6 PD I Shutdown input (active low)Power and Ground SignalsADC_PPA_LDO_OUT A8 O ADC/PPA LDO outputCL1.5_LDO_IN B6 I Power amplifier (PA) LDO inputConnect directly to batteryCL1.5_LDO_OUT A7 O PA LDO outputDCO_L
6、DO_OUT A12 O DCO LDO outputDIG_LDO_OUTA2, A3,B15,B26,B27,B35, B36ODigital LDO outputQFN pin B26 or B27 must be shortedto other DIG_LDO_OUT pins on thePCB.MLDO_IN B5 I Main LDO inputConnect directly to batteryMLDO_OUT A5, A9,B2, B7 I/O Main LDO output (1.8-V nominal)SRAM_LDO_OUT B1 O SRAM LDO output7
7、CC2564C ZHCSFX3A APRIL 2016REVISED NOVEMBER 2016Submit Documentation FeedbackProduct Folder Links: CC2564CTerminal Configuration and FunctionsCopyright 2016, Texas Instruments IncorporatedTable 4-1. Pin Attributes (VQFN-MR Package) (continued)NAME NO. PULL ATRESET DEF.DIR.(1) I/OType(2) DESCRIPTIONV
8、DD_IOA17,A34,A38,B18,B19,B21,B22, B25I I/O power supply (1.8-V nominal)VSS A24, A28 I GroundVSS_DCO B11 I DCO groundVSS_FREF B3 I Fast clock ground4.1.2 Connections for Unused Signals (VQFN-MR Package)Section 4.1.2 lists the connections for unused signals for the VQFN-MR package.SPACERFUNCTION PIN N
9、UMBER DESCRIPTIONNC A1 Not connectedNC A10 Not connectedNC A11 Not connectedNC A14 Not connectedNC A18 Not connectedNC A19 Not connectedNC A20 Not connectedNC A21 Not connectedNC A22 Not connectedNC A23 Not connectedNC A27 Not connectedNC A30 Not connectedNC A31 Not connectedNC A40 Not connectedNC B
10、9 Not connectedNC B10 Not connectedNC B16 Not connectedNC B17 Not connectedNC B20 Not connectedNC B23 Not connectedNC A13 TI internal useNC A15 TI internal useNC A16 TI internal useNC A36 TI internal useNC A37 TI internal useNC A39 TI internal useNC B12 TI internal useNC B13 TI internal useNC B14 TI
11、 internal useNC B29 TI internal useNC B30 TI internal useNC B31 TI internal useNC B28 TI internal use8CC2564CZHCSFX3A APRIL 2016REVISED NOVEMBER 2016 Submit Documentation FeedbackProduct Folder Links: CC2564CSpecifications Copyright 2016, Texas Instruments Incorporated(1) Stresses beyond those liste
12、d under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions f
13、or extended periods may affect device reliability.(2) Maximum allowed depends on accumulated time at that voltage: VDD_IN is defined in Section 7.1.(3) Analog pins: BT_RF, XTALP, and XTALM(4) The reference design supports a temperature range of 20C to +70C because of the operating conditions of the
14、crystal.5 SpecificationsUnless otherwise indicated, all measurements are taken at the device pins of the TI test evaluation board(EVB). All specifications are over process, voltage, and temperature, unless otherwise indicated.5.1 Absolute Maximum Ratings(1)Over operating free-air temperature range (
15、unless otherwise indicated). All parameters are measured as follows:VDD_IN = 3.6 V and VDD_IO = 1.8 V (unless otherwise indicated).MIN MAX UNITSupply voltage VDD_IN 0.5 4.8 V(2)VDDIO_1.8 V 0.5 2.145 VInput voltage to analog pins(3) 0.5 2.1 VInput voltage to all other pins 0.5 VDD_IO + 0.5 VBluetooth
16、 RF inputs 10 dBmOperating ambient temperature, TA(4) 40 85 CStorage temperature, Tstg 55 125 C(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD c
17、ontrol process.5.2 ESD RatingsVALUE UNITV(ESD) Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 500VCharged device model (CDM), per JEDEC specification JESD22-C101(2) 2505.3 Power-On HoursDEVICE CONDITIONS POWER-ON HOURSCC2564C Duty cycle = 25% active and 75% sleepTambien
18、t = 85C15,400 (7 years)9CC2564C ZHCSFX3A APRIL 2016REVISED NOVEMBER 2016Submit Documentation FeedbackProduct Folder Links: CC2564CSpecificationsCopyright 2016, Texas Instruments Incorporated(1) The device can be reliably operated for 7 years at Tambient of 85C, assuming 25% active mode and 75% sleep
19、 mode (15,400cumulative active power-on hours).(2) A crystal-based solution is limited by the temperature range required for the crystal to meet 20 ppm.5.4 Recommended Operating ConditionsMIN MAX UNITVDD_IN Power supply voltage 1.7 4.8 VVDD_IO I/O power supply voltage 1.62 1.92 VVIH High-level input
20、 voltage Default condition 0.65 VDD_IO VDD_IO VVIL Low-level input voltage Default condition 0 0.35 VDD_IO Vtr and tf I/O input rise and all times,10% to 90%asynchronous mode 1 10 nsI/O input rise and fall times,10% to 90%synchronous mode (PCM) 1 2.5 nsMaximum ripple on VDD_IN (sine wave) for1.8 V (
21、DC-DC) modeCondition: 0 to 0.1 MHz 60mVp-pCondition: 0.1 to 0.5 MHz 50Condition: 0.5 to 2.5 MHz 30Condition: 2.5 to 3.0 MHz 15Condition: 3.0 MHz 5Voltage dips on VDD_IN (VBAT)Duration = 577 s to 2.31 ms, period = 4.6 ms 400 mVMaximum ambient operating temperature(1) (2) 40 85 C5.5 Power Consumption
22、Summary5.5.1 Static Current Consumption(1) VBAT + VIO + VSHUTDOWN(2) VBAT + VIO(3) At maximum output power dBm(4) At maximum output power dBm(5) Both /4 DQPSK and 8DPSKOPERATIONAL MODE MIN TYP MAX UNITShutdown mode(1) 1 7 ADeep sleep mode(2) 40 105 ATotal I/O current consumption in active mode 1 mAC
23、ontinuous transmissionGFSK(3) 107 mAContinuous transmissionEDR(4)(5) 112.5 mA10CC2564CZHCSFX3A APRIL 2016REVISED NOVEMBER 2016 Submit Documentation FeedbackProduct Folder Links: CC2564CSpecifications Copyright 2016, Texas Instruments Incorporated5.5.2 Dynamic Current Consumption5.5.2.1 Current Consu
24、mption for Different Bluetooth BR and EDR ScenariosConditions: VDD_IN = 3.6 V, 25C, 26-MHz XTAL, nominal unit, 10-dBm output powerOPERATIONAL MODE MASTER AND SLAVE AVERAGE CURRENT UNITSCO link HV3 Master and slave 13.7 mAExtended SCO (eSCO) link EV3 64 kbps, no retransmission Master and slave 13.2 m
25、AeSCO link 2-EV3 64 kbps, no retransmission Master and slave 10 mAGFSK full throughput: TX = DH1, RX = DH5 Master and slave 40.5 mAEDR full throughput: TX = 2-DH1, RX = 2-DH5 Master and slave 41.2 mAEDR full throughput: TX = 3-DH1, RX = 3-DH5 Master and slave 41.2 mASniff, four attempts, 1.28 second
26、s Master and slave 145 APage or inquiry scan 1.28 seconds, 11.25 ms Master and slave 320 APage (1.28 seconds) and inquiry (2.56 seconds) scans,11.25 ms Master and slave 445 AA2DP source Master 13.9 mAA2DP sink Master 15.2 mAAssisted A2DP source Master 16.9 mAAssisted A2DP sink Master 18.1 mAAssisted
27、 WBS EV3; retransmit effort = 2;maximum latency = 8 ms Master and slave 17.5 and 18.5 mAAssisted WBS 2EV3; retransmit effort = 2;maximum latency = 12 ms Master and slave 11.9 and 13 mA5.5.2.2 Current Consumption for Different Low-Energy ScenariosConditions: VDD_IN = 3.6 V, 25C, nominal unit, 10-dBm
28、output powerMODE DESCRIPTION AVERAGECURRENT UNITAdvertising, nonconnectableAdvertising in all three channels1.28-seconds advertising interval15 bytes advertise data114 AAdvertising, discoverableAdvertising in all three channels1.28-seconds advertising interval15 bytes advertise data138 AScanningList
29、ening to a single frequency per window1.28-seconds scan interval11.25-ms scan window324 AConnectedMaster role 500-ms connection interval0-ms slave connection latencyEmpty TX and RX LL packets169ASlave role 19911CC2564C ZHCSFX3A APRIL 2016REVISED NOVEMBER 2016Submit Documentation FeedbackProduct Fold
30、er Links: CC2564CSpecificationsCopyright 2016, Texas Instruments Incorporated5.6 Electrical CharacteristicsRATING CONDITION MIN MAX UNITHigh-level output voltage, VOH At 2, 4, 8 mA 0.8 VDD_IO VDD_IO VAt 0.1 mA VDD_IO 0.2 VDD_IOLow-level output voltage, VOL At 2, 4, 8 mA 0 0.2 VDD_IO VAt 0.1 mA 0 0.2
31、I/O input impedance Resistance 1 MCapacitance 5 pFOutput rise and fall times, 10% to 90% (digital pins) CL = 20 pF 10 nsI/O pullcurrentsPCMI2S bus, TX_DBG PU Typical = 6.5 3.5 9.7APD Typical = 27 9.5 55All others PU Typical = 100 50 300PD Typical = 100 50 3605.7 Thermal Resistance Characteristics fo
32、r VQFN-MR (RVM) Package(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC RJC value, which is based on aJEDEC-defined 1S0P system) and will
33、change based on environment as well as application. For more information, see theseEIA/JEDEC standards: JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Package
34、s JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-9, Test Boards for Area Array Surface Mount Package Thermal MeasurementsPower dissipation of 2 W and an ambient temperature of 70C is assumed.over operating free-air temperature range (unless otherwis
35、e noted)THERMAL METRICS(1) C/W(2)Rja Junction-to-free-air 34.6Rjctop Junction-to-case-top 17.9Rjcbottom Junction-to-case-bottom 1.6Rjb Junction-to-board 12.0jt Junction-to-package-top 0.2jb Junction-to-package-bottom 12.012CC2564CZHCSFX3A APRIL 2016REVISED NOVEMBER 2016 Submit Documentation Feedback
36、Product Folder Links: CC2564CSpecifications Copyright 2016, Texas Instruments Incorporated5.8 Timing and Switching Characteristics5.8.1 Device Power SupplyThe CC2564C power-management hardware and software algorithms provide significant power savings,which is a critical parameter in an MCU-based sys
37、tem.The power-management module is optimized for drawing extremely low currents.5.8.1.1 Power SourcesThe CC2564C device requires two power sources: VDD_IN: main power supply for the device VDD_IO: power source for the 1.8-V I/O ringThe HCI module includes several on-chip voltage regulators for incre
38、ased noise immunity and can beconnected directly to the battery.5.8.1.2 Device Power-Up and Power-Down SequencingThe device includes the following power-up requirements (see Figure 5-1): nSHUTD must be low. VDD_IN and VDD_IO are dont care I/O pins when nSHUTD is low. However,signals are not allowed
39、on the I/O pins if I/O power is not supplied, because the I/Os are not fail-safe.Exceptions are SLOW_CLK_IN and AUD_xxx, which are fail-safe and can tolerate external voltageswith no VDD_IO and VDD_IN. VDD_IO and VDD_IN must be stable before releasing nSHUTD. The fast clock must be stable within 20
40、ms of nSHUTD going high. The slow clock must be stable within 2 ms of nSHUTD going high.The device indicates that the power-up sequence is complete by asserting RTS low, which occurs up to100 ms after nSHUTD goes high. If RTS does not go low, the device is not powered up. In this case,ensure that th
41、e sequence and requirements are met.nSHUTDVDD_IOHCI_RTS20 ms max20 s maxFAST CLOCKSLOW CLOCKCC256x readyVDD_IN2 ms max 100 msShut downbeforeVDD_IOremovedCopyright 2016, Texas Instruments Incorporated13CC2564C ZHCSFX3A APRIL 2016REVISED NOVEMBER 2016Submit Documentation FeedbackProduct Folder Links:
42、CC2564CSpecificationsCopyright 2016, Texas Instruments Incorporated(1) The terms None or Asserted can imply any of the following conditions: directly pulled to ground or driven low, pulled to ground through apulldown resistor, or left NC or floating (high-impedance output stage).Figure 5-1. Power-Up
43、 and Power-Down Sequencing5.8.1.3 Power Supplies and ShutdownStatic StatesThe nSHUTD signal puts the device in ultra-low-power mode and performs an internal reset to the device.The rise time for nSHUTD must not exceed 20 s; nSHUTD must be low for a minimum of 5 ms.To prevent conflicts with external
44、signals, all I/O pins are set to the high-impedance (Hi-Z) state duringshutdown and power up of the device. The internal pull resistors are enabled on each I/O pin, asdescribed in Section 4.1.1. Table 5-1 lists and describes the static operation states.Table 5-1. Power ModesVDD_IN (1) VDD_IO(1) nSHU
45、TD(1) PM_MODE COMMENTS1 None None Asserted Shutdown I/O state is undefined. No I/O voltagesare allowed on nonfail-safe pins.2 None None Deasserted Not allowed I/O state is undefined. No I/O voltagesare allowed on nonfail-safe pins.3 None Present Asserted Shutdown I/Os are defined as tri-state pins w
46、ithinternal pullup or pulldown enabled.4 None Present Deasserted Not allowed I/O state is undefined. No I/O voltagesare allowed on nonfail-safe pins.5 Present None Asserted Shutdown I/O state is undefined.6 Present None Deasserted Not allowed I/O state is undefined. No I/O voltagesare allowed on non
47、fail-safe pins.7 Present Present Asserted Shutdown I/Os are defined as tri-state pins withinternal pullup or pulldown enabled.8 Present Present Deasserted Active See Section 5.8.1.4.14CC2564CZHCSFX3A APRIL 2016REVISED NOVEMBER 2016 Submit Documentation FeedbackProduct Folder Links: CC2564CSpecificat
48、ions Copyright 2016, Texas Instruments Incorporated(1) I = input, O = output, Z = Hi-Z, = no pull, PU = pullup, PD = pulldown, H = high, L = low5.8.1.4 I/O States in Various Power ModesCAUTIONSome device I/Os are not fail-safe (see Section 4.1.1). Fail-safe means that thepins do not draw current fro
49、m an external voltage applied to the pin when I/Opower is not supplied to the device. External voltages are not allowed on theseI/O pins when the I/O supply voltage is not supplied because of possibledamage to the device.Table 5-2 lists the I/O states in various power modes.Table 5-2. I/O States in Various Power ModesI/O NAME SHUTDOWN(1) DEFAULT ACTIVE(1) DEEP SLEEP(1)I/O State Pull I/
