1、資訊學院研究能量與研發成果,Architecture and Systems 研究群報 告 人：單智君 陳昌居 鍾崇斌中華民國95年11月30日,資訊學院研究群,資訊科學與工程研究所研究群 architecture and systems鍾崇斌、單智君、陳昌居,Architecture and SystemsResearch Directions,Embedded processor and SoCJava processor, JIT compilation &VMDSP designs and compilationLow-power systemsGraphic processorSup
2、erscalar ARM processorReconfigurable computingAsynchronous circuits,Architecture and SystemsR&D Results,ARM9-compatible processor with video/audio capabilitiesJava stack operations foldingMemory Constrained Java Just-in-time CompilerAsynchronous 8051 for low-power SOC applicationsDSP instruction set
3、 extensions Low-power Branch-Target-Buffer Low-power bus encodingsLow-power cache memoryGraphic processor design techniquesSuperscalar ARM Reconfigurable computing,ARM9-compatible Processor with Audio/Video Capabilities,ARMAVP (ARM Audio Video Processor) 為32位元微處理器，採用負載平衡良好的五階管線設計，分別為 Fetch Unit、Deco
4、der Unit、Execution Unit、Memory access Unit 以及 Write Back Unit。對各階的設計進行效能的最佳化，以提高時脈頻率，並提供有效率的機制，降低了因為記憶體速度太慢對微處理機效能上的影響特性支援Conditional ExecutionABP 緩衝器設計改良指令抓取所需時間精確中斷控制結構非同步的記憶體存取 動態暫存器組的映射分支指令的快速處理多功能有效率的執行路徑分散式指令控制編碼功能驗證與評估所有功能已在Altera EP20K600EBC652-1上完成驗證。根據Decode Stage之模擬結果，在FPGA上可工作於45MHz，預期實做
5、為晶片時可達210MHz,Java Stack Operations Folding,JVM: Stack Based MachineJVM Performance Bottleneck: Stack Operation Dependency,Constant Register,(CR),Local Variable,(LV),Branch Unit,Complex Instr.,Local Variable,(LV),Execution Unit,Producer,(P),Operator,(O),Consumer,(C),Operand Stack,1,2,4,5,3,Constant R
6、egister,(CR),Local Variable,(LV),Branch Unit,Complex Instr.,Local Variable,(LV),Producer,(P),Operator,(O),Consumer,(C),Operand Stack,1=1 fold 2,5=4 fold 5,3,Before Folding,After Folding,Execution Unit,Memory Constrained Java Just-in-time Compiler,Mixed mode executionComplex bytecode is executed by t
7、he interpreterFast compilationTwo pass compilationSimple but effective optimizationsAbout 300 cycles per bytecodeSmall memory usageAbout 23KB for static footprint4KB code buffer is sufficient for common usage,Asynchronous 8051 for Low-Power SOC Applications,SA8051 (Balsa Asynchronous8051) 為一個8位元低耗電量
8、微控制器， 相容於Intel MCS-51，採用非同步 電路方式設計，動態耗電量約為 同步版本的三分之一。特性 - 無中央時脈 - 4-phase交握的設計 - soft-core 處理器 - 低耗電量 - 透過交握介面與同步IP整合 - 針對資料與控制路徑做最佳化功能驗證與評估所有功能已在Xilinx FPGA Spartan IIE 300 ft256上完成驗證。根據XPower之模擬結果，動態耗電量約為同步版本的三分之一。,DSP Instruction Set Extensions,Current directionsApplication-specific instruction s
9、et extensions (ISE) generationWhy ISE ?Improvement performance.Keep flexibility and efficiency of original processorWhat is ISE ?Group frequently executed instruction patterns to be an extended instructionExecuted in extra hardware, “Application Specific Functional Unit (ASFU)”,DSP Instruction Set E
10、xtensions (cont.),Current research topics Multiple-issue architectureExploring ISE in a multiple-issue architecture, such as superscalar or Very Long Instruction Word (VLIW)Hardware reusebilityReuse same or similar hardware resources in different ASFUs while keep same performance Overcome register f
11、ile read/write port constraintTry to schedule the input and output of ASFU at different time slots,BTB lookup operations of non-branch instructions are useless and only waste power,Branch Distance Generation and Collection將兩相鄰分支指令間的非分支指令個數蒐集紀錄。,Next Upcoming Branch Instruction Location取得下一道分支指令的位置並且
12、在其來臨前停止所有BTB Lookup動作。,Low-power Branch Target Buffer,Branch Distance Table,Low-power Bus Encodings,在此我們針對不同的匯流排架構的特性，提出了不同的低電耗匯流排編碼系統。我們的編碼系統利用了各種編碼方法，將藉由匯流排傳輸的資料，以最具有電耗效率的方式來傳送，達到省電的效果。低電耗匯流排編碼系統,Low-power Cache Memory,快取記憶體佔有整體處理器超過50%之功耗低功耗快取記憶體設計Loop Buffer: 將loop code置入低耗電存取之loop buffer中以節省指令擷
13、取之功耗Power Manager:將不常使用之快取記憶體區塊置入低耗電模式以節省快取記憶體之靜態功號。,Graphic Processor,1,2,3,4,5,研究目的進行新一代繪圖處理器架構研究，於像素著色器 (Pixel Shader)、材質 (Texture) 及深度處理 (Depth Processing) 等三大方向提出硬體架構及軟體驗證環境。目前成果分項說明如下,A dynamically reconfigurable graphics hardware for resource reallocatable rendering pipeline A Reconfigurable
14、Texture Mapping Architecture Implementation of texture Compression by GPU Driver Register Renaming for Pixel Shaders data/value managementInstruction scheduling mechanism for 3D GPU pixel shaderAn Efficient Texture Memory System DesignsAlpha Blending without Z Sort,6,Superscalar ARM,Goal: a supersca
15、lar embedded processor featuring800MHz clock rate 0.13um 1.8DMIPS / MHz superscalar performance under tough pipeline latency 800K gate count cost-effective designDirections and achievementsMicro-architectureA 12-stage dual-issue superscalar processor with good instruction fetch rate, issue rate, and
16、 efficient forwarding SimulatorA cycle-accurate simulator modeling more details than the well-known simplescalar simulatorCompilerWorking on GCC machine description to optimize performance,Reconfigurable Computing,Motivations:Improving the Design Methodology of Embedded System HardwareProviding a Be
17、tter Performance with Low Development Cost Shorting the Time-to-Market of SoC ProductsResearch Issues:Hardware/Software PartitionSynthesize TechnologyReconfigurable Processing Element Design,Reconfigurable Architecture,( 1 / 2 ),Reconfigurable Computing (cont.),( 2 / 2 ),Detailed Design of Reconfigurable Architecture,A Design of Reconfigurable Architecture,Scaleable Design of PE,Published Research Results: Run-time Reconfigurable Scheduling of 3D-Rendering on a Reconfigurable System (CCCT05) Design and Implementation of a Reconfigurable Hardware for Secure Embedded Systems (ASIACCS06),
