1、带有高阻态选通和复位控制的四选一多路选择器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX41A ISPORT(A,B,C,D,RST,EN:IN STD_LOGIC;S1,S0:IN STD_LOGIC;Y:OUT STD_LOGIC);END ENTITY MUX41A;ARCHITECTURE ONE OF MUX41A ISSIGNAL S1S0:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINS1S0YYYYY0);ELSIF CLKEVENT AND CLK=1 THENIF EN=1 THENQQ:=QQ+
2、1;IF QQ=“1111“ THEN COUT0);ELSIF CLKEVENT AND CLK=1 THENIF EN=1 THENQQ:=QQ-1;IF QQ=“0000“ THEN COUT0);ELSIF CLKEVENT AND CLK=1 THENIF EN=1 THENIF UPDOWN=1 THENQQ:=QQ+1;IF QQ=“1111“ THEN COUTDSDSDSDSNULL;END CASE;END PROCESS;END;全减器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY F_SUBER ISPORT(X,Y,SU
3、B_IN: IN STD_LOGIC;DIFFR,SUB_OUT:OUT STD_LOGIC);END;ARCHITECTURE ONE OF F_SUBER ISCOMPONENT H_SUBER PORT(X,Y: IN STD_LOGIC;DIFF,S_OUT:OUT STD_LOGIC);END COMPONENT;COMPONENT OR2A PORT(A,B: IN STD_LOGIC;C:OUT STD_LOGIC);END COMPONENT;SIGNAL A,B,C:STD_LOGIC;BEGINU1:H_SUBER PORT MAP (X=X,Y=Y,DIFF=A,S_OU
4、T=B);U2: H_SUBER PORT MAP (X=A,Y=SUB_IN,DIFF=DIFFR,S_OUT=C);U3: OR2A PORT MAP (A=C,B=B,C=SUB_OUT);END;八位寄存器的左右可控寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SHIIFT_L_R ISPORT(CLK,LOAD,UD: IN STD_LOGIC;DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);QB: OUT STD_LOGIC);END;ARCHITECTURE ONE OF SHIIFT_L_R ISBEGINPROCESS(CLK,LOAD,UD)VARIABLE REG8: STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINIF CLKEVENT AND CLK=1 THENIF LOAD=1 THEN REG8:=DIN;ELSEIF UD=1 THEN REG8(7 DOWNTO 1):=REG8(6 DOWNTO 0);QB=REG8(7);ELSE REG8(6 DOWNTO 0):=REG8(7 DOWNTO 1);QB=REG8(0);END IF;END IF;END IF;END PROCESS;END;
