MSP430G2553库函数.doc

1、/* Standard register and bit definitions for the Texas Instruments* MSP430 microcontroller.* This file supports assembler and C development for* MSP430G2553 devices.* Texas Instruments, Version 1.0* Rev. 1.0, Setup*/#ifndef _MSP430G2553#define _MSP430G2553#define _MSP430_HEADER_VERSION_ 1062#ifdef _

2、IAR_SYSTEMS_ICC_#ifndef _SYSTEM_BUILD#pragma system_include#endif#endif#if (_TID_ 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */#error msp430g2553.h file for use with ICC430/A430 only#endif#ifdef _IAR_SYSTEMS_ICC_#include in430.h#pragma language=extended#define DEFC(name, address) _no_init volatile unsigne

3、d char name address;#define DEFW(name, address) _no_init volatile unsigned short name address;#define DEFXC volatile unsigned char#define DEFXW volatile unsigned short#endif /* _IAR_SYSTEMS_ICC_ */#ifdef _IAR_SYSTEMS_ASM_#define DEFC(name, address) sfrb name = address;#define DEFW(name, address) sfr

4、w name = address;#endif /* _IAR_SYSTEMS_ASM_*/#ifdef _cplusplus#define READ_ONLY#else#define READ_ONLY const#endif/* STANDARD BITS*/#define BIT0 (0x0001u)#define BIT1 (0x0002u)#define BIT2 (0x0004u)#define BIT3 (0x0008u)#define BIT4 (0x0010u)#define BIT5 (0x0020u)#define BIT6 (0x0040u)#define BIT7 (

5、0x0080u)#define BIT8 (0x0100u)#define BIT9 (0x0200u)#define BITA (0x0400u)#define BITB (0x0800u)#define BITC (0x1000u)#define BITD (0x2000u)#define BITE (0x4000u)#define BITF (0x8000u)/* STATUS REGISTER BITS*/#define C (0x0001u)#define Z (0x0002u)#define N (0x0004u)#define V (0x0100u)#define GIE (0x

6、0008u)#define CPUOFF (0x0010u)#define OSCOFF (0x0020u)#define SCG0 (0x0040u)#define SCG1 (0x0080u)/* Low Power Modes coded with Bits 4-7 in SR */#ifndef _IAR_SYSTEMS_ICC_ /* Begin #defines for assembler */#define LPM0 (CPUOFF)#define LPM1 (SCG0+CPUOFF)#define LPM2 (SCG1+CPUOFF)#define LPM3 (SCG1+SCG

7、0+CPUOFF)#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)/* End #defines for assembler */#else /* Begin #defines for C */#define LPM0_bits (CPUOFF)#define LPM1_bits (SCG0+CPUOFF)#define LPM2_bits (SCG1+CPUOFF)#define LPM3_bits (SCG1+SCG0+CPUOFF)#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)#include in430.h#defin

8、e LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power

9、 Mode 2 */#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */#define LPM4_EXIT _BIC_SR_IRQ(LPM4

10、_bits) /* Exit Low Power Mode 4 */#endif /* End #defines for C */* PERIPHERAL FILE MAP*/* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS*/#define IE1_ (0x0000u) /* Interrupt Enable 1 */DEFC( IE1 , IE1_)#define WDTIE (0x01) /* Watchdog Interrupt Enable */#define OFIE (0x02) /* Osc. Fault Interrup

11、t Enable */#define NMIIE (0x10) /* NMI Interrupt Enable */#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */#define IFG1_ (0x0002u) /* Interrupt Flag 1 */DEFC( IFG1 , IFG1_)#define WDTIFG (0x01) /* Watchdog Interrupt Flag */#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */#define

12、 PORIFG (0x04) /* Power On Interrupt Flag */#define RSTIFG (0x08) /* Reset Interrupt Flag */#define NMIIFG (0x10) /* NMI Interrupt Flag */#define IE2_ (0x0001u) /* Interrupt Enable 2 */DEFC( IE2 , IE2_)#define UC0IE IE2#define UCA0RXIE (0x01)#define UCA0TXIE (0x02)#define UCB0RXIE (0x04)#define UCB0

13、TXIE (0x08)#define IFG2_ (0x0003u) /* Interrupt Flag 2 */DEFC( IFG2 , IFG2_)#define UC0IFG IFG2#define UCA0RXIFG (0x01)#define UCA0TXIFG (0x02)#define UCB0RXIFG (0x04)#define UCB0TXIFG (0x08)/* ADC10*/#define _MSP430_HAS_ADC10_ /* Definition to show that Module is available */#define ADC10DTC0_ (0x0

14、048u) /* ADC10 Data Transfer Control 0 */DEFC( ADC10DTC0 , ADC10DTC0_)#define ADC10DTC1_ (0x0049u) /* ADC10 Data Transfer Control 1 */DEFC( ADC10DTC1 , ADC10DTC1_)#define ADC10AE0_ (0x004Au) /* ADC10 Analog Enable 0 */DEFC( ADC10AE0 , ADC10AE0_)#define ADC10CTL0_ (0x01B0u) /* ADC10 Control 0 */DEFW(

15、 ADC10CTL0 , ADC10CTL0_)#define ADC10CTL1_ (0x01B2u) /* ADC10 Control 1 */DEFW( ADC10CTL1 , ADC10CTL1_)#define ADC10MEM_ (0x01B4u) /* ADC10 Memory */DEFW( ADC10MEM , ADC10MEM_)#define ADC10SA_ (0x01BCu) /* ADC10 Data Transfer Start Address */DEFW( ADC10SA , ADC10SA_)/* ADC10CTL0 */#define ADC10SC (0

16、x001) /* ADC10 Start Conversion */#define ENC (0x002) /* ADC10 Enable Conversion */#define ADC10IFG (0x004) /* ADC10 Interrupt Flag */#define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */#define ADC10ON (0x010) /* ADC10 On/Enable */#define REFON (0x020) /* ADC10 Reference on */#define REF2_5V (0x040)

17、 /* ADC10 Ref 0:1.5V / 1:2.5V */#define MSC (0x080) /* ADC10 Multiple SampleConversion */#define REFBURST (0x100) /* ADC10 Reference Burst Mode */#define REFOUT (0x200) /* ADC10 Enalbe output of Ref. */#define ADC10SR (0x400) /* ADC10 Sampling Rate 0:200ksps / 1:50ksps */#define ADC10SHT0 (0x800) /*

18、 ADC10 Sample Hold Select Bit: 0 */#define ADC10SHT1 (0x1000u) /* ADC10 Sample Hold Select Bit: 1 */#define SREF0 (0x2000u) /* ADC10 Reference Select Bit: 0 */#define SREF1 (0x4000u) /* ADC10 Reference Select Bit: 1 */#define SREF2 (0x8000u) /* ADC10 Reference Select Bit: 2 */#define ADC10SHT_0 (0*0

19、x800u) /* 4 x ADC10CLKs */#define ADC10SHT_1 (1*0x800u) /* 8 x ADC10CLKs */#define ADC10SHT_2 (2*0x800u) /* 16 x ADC10CLKs */#define ADC10SHT_3 (3*0x800u) /* 64 x ADC10CLKs */#define SREF_0 (0*0x2000u) /* VR+ = AVCC and VR- = AVSS */#define SREF_1 (1*0x2000u) /* VR+ = VREF+ and VR- = AVSS */#define

20、SREF_2 (2*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */#define SREF_3 (3*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */#define SREF_4 (4*0x2000u) /* VR+ = AVCC and VR- = VREF-/VEREF- */#define SREF_5 (5*0x2000u) /* VR+ = VREF+ and VR- = VREF-/VEREF- */#define SREF_6 (6*0x2000u) /* VR+ = VEREF+ and VR- = VR

21、EF-/VEREF- */#define SREF_7 (7*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */* ADC10CTL1 */#define ADC10BUSY (0x0001u) /* ADC10 BUSY */#define CONSEQ0 (0x0002u) /* ADC10 Conversion Sequence Select 0 */#define CONSEQ1 (0x0004u) /* ADC10 Conversion Sequence Select 1 */#define ADC10SSEL0 (0x0008u)

22、/* ADC10 Clock Source Select Bit: 0 */#define ADC10SSEL1 (0x0010u) /* ADC10 Clock Source Select Bit: 1 */#define ADC10DIV0 (0x0020u) /* ADC10 Clock Divider Select Bit: 0 */#define ADC10DIV1 (0x0040u) /* ADC10 Clock Divider Select Bit: 1 */#define ADC10DIV2 (0x0080u) /* ADC10 Clock Divider Select Bit

23、: 2 */#define ISSH (0x0100u) /* ADC10 Invert Sample Hold Signal */#define ADC10DF (0x0200u) /* ADC10 Data Format 0:binary 1:2s complement */#define SHS0 (0x0400u) /* ADC10 Sample/Hold Source Bit: 0 */#define SHS1 (0x0800u) /* ADC10 Sample/Hold Source Bit: 1 */#define INCH0 (0x1000u) /* ADC10 Input C

24、hannel Select Bit: 0 */#define INCH1 (0x2000u) /* ADC10 Input Channel Select Bit: 1 */#define INCH2 (0x4000u) /* ADC10 Input Channel Select Bit: 2 */#define INCH3 (0x8000u) /* ADC10 Input Channel Select Bit: 3 */#define CONSEQ_0 (0*2u) /* Single channel single conversion */#define CONSEQ_1 (1*2u) /*

25、 Sequence of channels */#define CONSEQ_2 (2*2u) /* Repeat single channel */#define CONSEQ_3 (3*2u) /* Repeat sequence of channels */#define ADC10SSEL_0 (0*8u) /* ADC10OSC */#define ADC10SSEL_1 (1*8u) /* ACLK */#define ADC10SSEL_2 (2*8u) /* MCLK */#define ADC10SSEL_3 (3*8u) /* SMCLK */#define ADC10DI

26、V_0 (0*0x20u) /* ADC10 Clock Divider Select 0 */#define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select 1 */#define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select 2 */#define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select 3 */#define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select 4 */

27、#define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select 5 */#define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select 6 */#define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select 7 */#define SHS_0 (0*0x400u) /* ADC10SC */#define SHS_1 (1*0x400u) /* TA3 OUT1 */#define SHS_2 (2*0x400u) /* TA3 OU

28、T0 */#define SHS_3 (3*0x400u) /* TA3 OUT2 */#define INCH_0 (0*0x1000u) /* Selects Channel 0 */#define INCH_1 (1*0x1000u) /* Selects Channel 1 */#define INCH_2 (2*0x1000u) /* Selects Channel 2 */#define INCH_3 (3*0x1000u) /* Selects Channel 3 */#define INCH_4 (4*0x1000u) /* Selects Channel 4 */#defin

29、e INCH_5 (5*0x1000u) /* Selects Channel 5 */#define INCH_6 (6*0x1000u) /* Selects Channel 6 */#define INCH_7 (7*0x1000u) /* Selects Channel 7 */#define INCH_8 (8*0x1000u) /* Selects Channel 8 */#define INCH_9 (9*0x1000u) /* Selects Channel 9 */#define INCH_10 (10*0x1000u) /* Selects Channel 10 */#de

30、fine INCH_11 (11*0x1000u) /* Selects Channel 11 */#define INCH_12 (12*0x1000u) /* Selects Channel 12 */#define INCH_13 (13*0x1000u) /* Selects Channel 13 */#define INCH_14 (14*0x1000u) /* Selects Channel 14 */#define INCH_15 (15*0x1000u) /* Selects Channel 15 */* ADC10DTC0 */#define ADC10FETCH (0x00

31、1) /* This bit should normally be reset */#define ADC10B1 (0x002) /* ADC10 block one */#define ADC10CT (0x004) /* ADC10 continuous transfer */#define ADC10TB (0x008) /* ADC10 two-block mode */#define ADC10DISABLE (0x000) /* ADC10DTC1 */* Basic Clock Module*/#define _MSP430_HAS_BC2_ /* Definition to

32、show that Module is available */#define DCOCTL_ (0x0056u) /* DCO Clock Frequency Control */DEFC( DCOCTL , DCOCTL_)#define BCSCTL1_ (0x0057u) /* Basic Clock System Control 1 */DEFC( BCSCTL1 , BCSCTL1_)#define BCSCTL2_ (0x0058u) /* Basic Clock System Control 2 */DEFC( BCSCTL2 , BCSCTL2_)#define BCSCTL

33、3_ (0x0053u) /* Basic Clock System Control 3 */DEFC( BCSCTL3 , BCSCTL3_)#define MOD0 (0x01) /* Modulation Bit 0 */#define MOD1 (0x02) /* Modulation Bit 1 */#define MOD2 (0x04) /* Modulation Bit 2 */#define MOD3 (0x08) /* Modulation Bit 3 */#define MOD4 (0x10) /* Modulation Bit 4 */#define DCO0 (0x20

34、) /* DCO Select Bit 0 */#define DCO1 (0x40) /* DCO Select Bit 1 */#define DCO2 (0x80) /* DCO Select Bit 2 */#define RSEL0 (0x01) /* Range Select Bit 0 */#define RSEL1 (0x02) /* Range Select Bit 1 */#define RSEL2 (0x04) /* Range Select Bit 2 */#define RSEL3 (0x08) /* Range Select Bit 3 */#define DIVA

35、0 (0x10) /* ACLK Divider 0 */#define DIVA1 (0x20) /* ACLK Divider 1 */#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */#define XT2OFF (0x80) /* Enable XT2CLK */#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */#define DIVS0 (0x02) /* SMCLK Divider 0 */#define DIVS1 (0x04) /* SMCLK Divider 1 */#define SELS