1、GNDOUTINFSLVCMOSControlLogicOELVCMOSVDDSSC_SEL 0SSC_SEL 1x1orx4/SSC1 82 73 64 5CDCS503-Q1INSSC_SEL0SSC_SEL1GNDVDDOEOUTFSCDCS503-Q ZHCS946B MARCH 2012REVISED JUNE 2012带带有有可可选选展展频频时时钟钟(SSC)的的时时钟钟缓缓冲冲器器/时时钟钟倍倍乘乘器器查查询询样样品品: CDCS503-Q11特特性性符符合合汽汽车车应应用用要要求求单单一一3.3V器器件件电电源源具具有有下下列列结结果果的的AEC-Q100测测试试指指南南：宽宽
2、温温度度范范围围-40C至至105C器器件件温温度度2级级节节省省空空间间的的8引引脚脚薄薄型型小小外外形形尺尺寸寸(TSSOP)封封装装 -40C至至105C环环境境温温度度范范围围应应用用范范围围器器件件人人体体模模型型(HBM)静静电电放放电电(ESD)分分类类等等级级要要求求通通过过SSC和和/或或者者时时钟钟倍倍乘乘来来减减少少电电磁磁干干扰扰H2(EMI)的的车车载载应应用用器器件件充充电电器器件件模模型型(CDM) ESD分分类类等等级级C3B带带有有可可选选展展频频时时钟钟(SSC)的的易易于于使使用用的的时时钟钟生生成成器器产产品品的的一一部部分分带带有有可可选选输输出出频频
3、率率和和可可选选SSC的的时时钟钟倍倍乘乘器器通通过过两两个个外外部部引引脚脚可可控控制制SSC 0%，0.5%，1%，2%中中心心展展频频可可使使用用一一个个外外部部控控制制引引脚脚来来选选择择x1或或者者x4的的频频率率倍倍乘乘通通过过控控制制引引脚脚进进行行输输出出禁禁用用图图1.方方框框图图1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconduct
4、or products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.版权 2012, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does not En
5、glish Data Sheet: SCAS924necessarily include testing of all parameters.CDCS503-Q1ZHCS946B MARCH 2012REVISED JUNE 2012 说说明明CDCS503-Q1是一款带有可选频率倍乘的可展频、LVCMOS输入时钟缓冲器。它与CDCS502共用主要的功能性，但是它使用一个LVCMOS输入级而不是CDCS502所使用的晶振输入级，并且CDCS503-Q1有一个输出使能引脚。此器件在输入上接受一个3.3V LVCMOS信号。这个输入信号由一个锁相环路(PLL)处理，此环路的输出频率或者与输入频率相
6、等或者被乘以因子4。PLL还可通过三角调制将时钟信号以输出时钟频率为中心扩展0%，0.5%，1%或者2%。这样，此器件可生成介于8MHz和108MHz之间带有或者不带有SSC的输出频率。一个独立的控制引脚可被用于启用或者禁用输出。CDCS503-Q1运行在一个3.3V环境中。器件额定运行温度介于-40C至105C之间，并采用8引脚TSSOP封装。表表1.功功能能表表OE FS SSC_SEL 0 SSC_SEL 1 SSC数数量量fOUT/fIN fin=27MHz时时的的fOUT0 x x x x x三态1 0 0 0 0.00% 1 27MHz1 0 0 1 0.50% 1 27MHz1
7、0 1 0 1.00% 1 27MHz1 0 1 1 2.00% 1 27MHz1 1 0 0 0.00% 4 108MHz1 1 0 1 0.50% 4 108MHz1 1 1 0 1.00% 4 108MHz1 1 1 1 2.00% 4 108MHz2版权 2012, Texas Instruments Incorporated1 82 73 64 5CDCS503-Q1INSSC_SEL0SSC_SEL1GNDVDDOEOUTFSCDCS503-Q ZHCS946B MARCH 2012REVISED JUNE 2012这些装置包含有限的内置ESD保护。存储或装卸时，应将导线一起截短或
8、将装置放置于导电泡棉中，以防止MOS门极遭受静电损伤。DEVICE INFORMATIONPACKAGEPIN FUNCTIONSSIGNAL PIN TYPE DESCRIPTIONIN 1 I LVCMOS clock inputOUT 6 O LVCMOS clock outputSSC_SEL 0, 1 2, 3 I Spread selection pins, internal pullupOE 7 I Output enable, internal pullupFS 5 I Frequency multiplication selection, internal pullupVDD
9、 8 Power 3.3-V power supplyGND 4 Ground GroundORDERING INFORMATIONTA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING40C to 105C TSSOP 2000 CDCS503TPWRQ1 CS503QPACKAGE THERMAL RESISTANCE FOR TSSOP (PW) PACKAGEover operating free-air temperature range (unless otherwise noted)(1)THERMAL AIRFLOW (CFM)PW
10、8-PIN TSSOP UNIT0 150 250 500High K 149 142 138 132RJA C/WLow K 230 185 170 150High K 65RJC C/WLow K 69(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).THERMAL INFORMATIONCDCS503TPWRQ1THERMAL METRIC(1) UNITPW (8 PINS)JA Junction-to-ambient therm
11、al resistance 179.9JCtop Junction-to-case (top) thermal resistance 64.9JB Junction-to-board thermal resistance 108.7 C/WJT Junction-to-top characterization parameter 9JB Junction-to-board characterization parameter 107JCbot Junction-to-case (bottom) thermal resistance n/a(1)有关传统和全新热度量的更多信息，请参阅IC封装热度
12、量应用报告（文献号：SPRA953）。Copyright 2012, Texas Instruments Incorporated 3CDCS503-Q1ZHCS946B MARCH 2012REVISED JUNE 2012 ABSOLUTE MAXIMUM RATINGS(1)over operating free-air temperature range (unless otherwise noted)VALUE UNITVDD Supply voltage range 0.5 to 4.6 VVIN Input voltage range 0.5 to 4.6 VVout Outpu
13、t voltage range 0.5 to 4.6 VIIN Input current (VI VDD) 20 mAIout Continuous output current 50 mATST Storage temperature range 65 to 150 CTJ Maximum junction temperature 125 CESD Rating Human-body model (HBM) AEC-Q100 classification level H2 1.5 kVCharged-device model (CDM) AEC-Q100 classification le
14、vel C3B 750 V(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exp
15、osure to absolute-maximum-rated conditions for extended periods may affect device reliability.4 Copyright 2012, Texas Instruments IncorporatedCDCS503-Q ZHCS946B MARCH 2012REVISED JUNE 2012RECOMMENDED OPERATING CONDITIONSMIN NOM MAX UNITVDD Supply voltage 3 3.6 VFS = 0 8 32fIN Input frequency MHzFS =
16、 1 8 27VIL Low-level input voltage LVCMOS 0.3 VDD VVIH High-level input voltage LVCMOS 0.7 VDD VVI Input voltage threshold LVCMOS 0.5 VDD VCL Output load test LVCMOS 15 pFIOH/IOL Output current 12 mATA Operating free-air temperature 40 105 CDEVICE CHARACTERISTICSover recommended operating free-air t
17、emperature range (unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITfout = 20 MHz; FS = 0, no SSC 19IDD Device supply current mAfout = 70 MHz; FS = 1, SSC = 2% 22FS = 0 8 32fOUT Output frequency MHzFS = 1 32 108IIH LVCMOS input current VI = VDD; VDD = 3.6 V 10 AIIL LVCMOS input curren
18、t VI = 0 V; VDD = 3.6 V 10 AIOH = - 0.1 mA 2.9VOH LVCMOS high-level output voltage IOH = - 8 mA 2.4 VIOH = - 12 mA 2.2IOL = 0.1 mA 0.1VOL LVCMOS low-level output voltage IOL = 8 mA 0.5 VIOL = 12 mA 0.8IOZ High-impedance-state output current OE = Low 2 2 AtJIT(C-C) Cycle to cycle jitter(1) fout = 108
19、 MHz; FS = 1, 110 psSSC = 1%, 10000 Cyclestr/tf Rise and fall time(1) 20%80% 0.75 nsOdc Output duty cycle(2) 45% 55%fMOD Modulation frequency 30 kHz(1) Measured with Test Load, see Figure 3.(2) Not production tested.Copyright 2012, Texas Instruments Incorporated 5VDD1 kc87CDCS503-Q1LVCMOS1 kc87 10 p
20、F05101520253035400 5 10 15 20 25 30 35f -InputFrequency-MHzix1Modex4ModeI-InputCurrent-mADDCDCS503-Q1ZHCS946B MARCH 2012REVISED JUNE 2012 Figure 2. IDD vs Input Frequency, VCC = 3.3 V, SSC = 2%,Output Loaded With Test LoadAPPLICATION INFORMATIONSSC MODULATIONThe exact implementation of the SSC modul
21、ation plays a vital role for the EMI reduction. The CDCS503-Q1device uses a triangular modulation scheme implemented in a way that the modulation frequency depends onthe VCO frequency of the internal PLL and the spread amount is independent from the VCO frequency.The modulation frequency can be calc
22、ulated by using one of the below formulas chosen by frequencymultiplication mode.FS = 0: fmod = fIN / 708FS = 1: fmod = fIN / 620PARAMETER MEASUREMENT INFORMATIONFigure 3. Test Load6 Copyright 2012, Texas Instruments IncorporatedLVCMOS LVCMOSCDCS503-Q1Typical DriverImpedance 32 c87Series Termination
23、 18 c87Z = 50L c87CDCS503-Q ZHCS946B MARCH 2012REVISED JUNE 2012PARAMETER MEASUREMENT INFORMATION (continued)Figure 4. Load for 50- Board EnvironmentCopyright 2012, Texas Instruments Incorporated 7CDCS503-Q1ZHCS946B MARCH 2012REVISED JUNE 2012 REVISION HISTORYChanges from Revision A (June 2012) to R
24、evision B Page在FAD中将符合AEC Q100标准改为了AEC Q100测试指南. 18 Copyright 2012, Texas Instruments IncorporatedPACKAGE OPTION ADDENDUM 11-Apr-2013Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)Op Temp (C) Top-Sid
25、e Markings(4)SamplesCDCS503TPWRQ1 ACTIVE TSSOP PW 8 2000 Green (RoHS& no Sb/Br)CU NIPDAU Level-3-260C-168 HR -40 to 105 CS503Q(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and
26、a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has
27、 discontinued the production of the device.(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http:/ for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion p
28、lan has not been defined.Pb-Free (RoHS): TIs terms “Lead-Free“ or “Pb-Free“ mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at
29、 high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe.
30、The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines “Green“ to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)(3) MSL, Pea
31、k Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a “ will appear on a device. If a line
32、is indented then it is acontinuation of the previous line and the two combined represent the entire Top-Side Marking for that device.Important Information and Disclaimer:The information provided on this page represents TIs knowledge and belief as of the date that it is provided. TI bases its knowled
33、ge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate in
34、formation but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TIs liability ar
35、ising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.OTHER QUALIFIED VERSIONS OF CDCS503-Q1 : Catalog: CDCS503PACKAGE OPTION ADDENDUM 11-Apr-2013Addendum-Page 2NOTE: Qualified Version Definitions: Catalog
36、- TIs standard catalog productTAPE AND REEL INFORMATION*All dimensions are nominalDevice PackageTypePackageDrawingPins SPQ ReelDiameter(mm)ReelWidthW1 (mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantCDCS503TPWRQ1 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1PACKAGE MATERIALS INFORMATION 29-Apr-201
37、6Pack Materials-Page 1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)CDCS503TPWRQ1 TSSOP PW 8 2000 367.0 367.0 35.0PACKAGE MATERIALS INFORMATION 29-Apr-2016Pack Materials-Page PACKAGE OUTLINECTYP6.66.21.2 MAX6X 0.658X 0.300.192X1.950.150.05(
38、0.15) TYP0 - 80.25GAGE PLANE0.750.50ANOTE 33.12.9BNOTE 44.54.34221848/A 02/2015TSSOP - 1.2 mm max heightPW0008ASMALL OUTLINE PACKAGENOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancingper ASME Y14.5M. 2. This drawing i
39、s subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall notexceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.5. Reference J
40、EDEC registration MO-153, variation AA.180.1 C A B54PIN 1 IDAREASEATING PLANE0.1 CSEE DETAIL ADETAIL ATYPICALSCALE EXAMPLE BOARD LAYOUT(5.8)0.05 MAXALL AROUND0.05 MINALL AROUND8X (1.5)8X (0.45)6X (0.65)(R )TYP0.054221848/A 02/2015TSSOP - 1.2 mm max heightPW0008ASMALL OUTLINE PACKAGESYMMSYMMLAND PATT
41、ERN EXAMPLESCALE:10X1458NOTES: (continued)6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.METALSOLDER MASKOPENINGNON SOLDER MASKDEFINEDSOLDER MASK DETAILSNOT TO SCALESOLDER MASKOPENINGMETAL UNDERSOL
42、DER MASKSOLDER MASKDEFINEDEXAMPLE STENCIL DESIGN(5.8)6X (0.65)8X (0.45)8X (1.5)(R ) TYP0.054221848/A 02/2015TSSOP - 1.2 mm max heightPW0008ASMALL OUTLINE PACKAGENOTES: (continued)8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have a
43、lternatedesign recommendations. 9. Board assembly site may have different recommendations for stencil design.SYMMSYMM1458SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCILSCALE:10X重重要要声声明明德州仪器(TI)及其下属子公司有权根据JESD46最新标准,对所提供的产品和服务进行更正、修改、增强、改进或其它更改，并有权根据JESD48最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息,并验证这些信息
44、是否完整且是最新的。所有产品的销售都遵循在订单确认时所提供的TI销售条款与条件。TI保证其所销售的组件的性能符合产品销售时TI半导体产品销售条件与条款的适用规范。仅在TI保证的范围内，且TI认为有必要时才会使用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。TI对应用帮助或客户产品设计不承担任何义务。客户应对其使用TI组件的产品和应用自行负责。为尽量减小与客户产品和应用相关的风险，客户应提供充分的设计与操作安全措施。TI不对任何TI专利权、版权、屏蔽作品权或其它与使用了TI组件或服务的组合设备、机器或流程相关的TI知识产权中授予的直接或隐含权限作出
45、任何保证或解释。TI所发布的与第三方产品或服务有关的信息，不能构成从TI获得使用这些产品或服务的许可、授权、或认可。使用此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是TI的专利权或其它知识产权方面的许可。对于TI的产品手册或数据表中TI信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况下才允许进行复制。TI对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。在转售TI组件或服务时，如果对该组件或服务参数的陈述与TI标明的参数相比存在差异或虚假成分，则会失去相关TI组件或服务的所有明示或暗示授权，且这是不正当的、欺诈
46、性商业行为。TI对任何此类虚假陈述均不承担任何责任或义务。客户认可并同意，尽管任何应用相关信息或支持仍可能由TI提供，但他们将独力负责满足与其产品及在其应用中使用TI产品相关的所有法律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见故障的危险后果、监测故障及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因在此类安全关键应用中使用任何TI组件而对TI及其代理造成的任何损失。在某些场合中，为了推进安全相关应用有可能对TI组件进行特别的促销。TI的目标是利用此类组件帮助客户设计和创立其特有的可满足适用的功能安全性标准
47、和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。TI组件未获得用于FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使用的特别协议。只有那些TI特别注明属于军用等级或“增强型塑料”的TI组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同意，对并非指定面向军事或航空航天用途的TI组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独力负责满足与此类使用相关的所有法律和法规要求。TI已明确指定符合ISO/TS16949要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到ISO/TS16949要求，TI不承担任何责任。产产品品应应用用数字音频 -数字信号处理器
