1、 ASIX ELECTRONICS CORPORATION Released Date: 08/10/2011 4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsin-Chu City, Taiwan, R.O.C. 300 TEL: 886-3-579-9500 FAX: 886-3-579-9558 http:/.tw/ AX88772BLF / AX88772BLILow-PowerUSB 2.0 to 10/100M Fast Ethernet ControllerFeatures Single chip USB 2.0 to 10/100
2、M Fast Ethernet controller Single chip USB 2.0 to RMII, support HomePNAand HomePlug PHY Single chip USB 2.0 to Reverse-RMII, supports glueless MAC-to-MAC connections USB Device Interface Integrates on-chip USB 2.0 transceiver and SIE compliant to USB Spec 1.1 and 2.0 Supports USB Full and High Speed
3、 modes with Bus-Power or Self-Power capability Supports 4 or 6 programmable endpoints on USB interface Supports AutoDetach power saving. Detach from USB host when Ethernet cable is unplugged High performance packet transfer rate over USB bus using proprietary burst transfer mechanism (US Patent Appr
4、oval) Fast Ethernet Controller Integrates 10/100Mbps Fast Ethernet MAC/PHY IEEE 802.3 10BASE-T/100BASE-TX compatible IEEE 802.3 100BASE-FX compatible Supports twisted pair crossover detection and auto-correction (HP Auto-MDIX) Embedded SRAM for RX/TX packet buffering Supports IPv4/ IPv6 packet Check
5、sum Offload Engine(COE) to reduce CPU loading, including IPv4 IP/TCP/UDP/ICMP/IGMP please refer to section 2.2 Settings. 13AX88772BLF / AX88772BLI Low-power USB 2.0 to 10/100M Fast Ethernet ControllerCopyright 2010-2010 ASIX Electronics Corporation. All rights reserved. GPIO_0/PME B5/PD 27 General P
6、urpose Input/ Output Pin 0 or PME (Power Management Event).This pin is default as input pin after power-on reset. GPIO_0 also can be defined as PME output to indicate wake up event detected. Please refer to section 2.2 Settings. MFB7 B5/PUI5 I5 28 This is a multi-function pin. Please refer to sectio
7、n 2.2 Settings. MFB7: RMII : RXD0 Reverse_RMII : TXD0 MFB6 B5/PUI5 I5 29 This is a multi-function pin. Please refer to section 2.2 Settings. MFB6: RMII : RXD1 Reverse_RMII : TXD1 MFB5/ REF50 B5/PUB5 30 This is a multi-function pin. Please refer to section 2.2 Settings. MFB5: When RMII enable, The RE
8、F50 in/out direction is determined by EEPROM Flag 1 setting. Please refer to section 2.2 Settings. MFB4 B5/PUO3 O3 31 This is a multi-function pin. Please refer to section 2.2 Settings. RMII : TXD0 Reverse_RMII : RXD0 MFB3 B5/PUO3 O3 32 This is a multi-function pin. Please refer to section 2.2 Setti
9、ngs. RMII : TXD1 Reverse_RMII : RXD1 MFB2 B5/PUO3 O3 33 This is a multi-function pin. Please refer to section 2.2 Settings. RMII : TXEN Reverse_RMII : CRSDV MFB1 B5/PUI5 I5 34 This is a multi-function pin. Please refer to section 2.2 Settings. RMII : CRSDV Reverse_RMII : TXEN MFB0 B5/PU 35 This is a
10、 GPIO pin. Please refer to section 2.2 Settings. MFA3/ PHY_N O3 I5/PU 21 It is a multi-function pin. The default is USB Speed indicator. When USB bus is in Full speed, this pin will tri-state continuously. When USB bus is in High speed, this pin drives low continuously. This pin tri-state and drive
11、low in turn (blinking) to indicate TX data transfer going on whenever the host controller sends bulk out data transfer. MFB17 bus is determined by setting of this input pin when MFA2 sets 0:0: Reverse_RMII (PHY mode). 1: RMII (MAC mode). Please refer to PIN configuration of MFA and MFB in section 2.
12、2 Settings.MFA2/ RMII_N O3 I5/PU 19 It is a multi-function pin. The default is Link status LED indicator. This pin drives low continuously when the Ethernet link is up and drives low and high in turn (blinking) when Ethernet PHY is in receiving or transmitting state. MFB17 function is determined by
13、setting of this input pin: 0: Reverse_RMII/RMII . 1: MFB bus as GPIO function. Please refer to PIN configuration of MFA and MFB in section 2.2 Settings.MFA1/ MDIO O3 B5/PU18 It is a multi-function pin. The default is Ethernet speed LED indicator. This pin drives low when the Ethernet PHY is in 100BA
14、SE-TX mode and drives high when in 10BASE-T mode. This pin can perform as MDIO when enabling Reverse_RMII/RMII. 14AX88772BLF / AX88772BLI Low-power USB 2.0 to 10/100M Fast Ethernet ControllerCopyright 2010-2010 ASIX Electronics Corporation. All rights reserved. MFA0/ MDC O3 O3 I5/PU 17 It is a multi
15、-function pin. The default is Full Duplex and collision detectedLED indicator. This pin drives low when the Ethernet PHY is in full-duplex mode and drives high when in half duplex mode. When in half duplex mode and the Ethernet PHY detects collision, it will be driven low (or blinking). This pin can
16、 perform as MDC when enabling Reverse_RMII/RMII: RMII : Output. Reverse_RMII : Input. SD I 7 Fiber signal detected Twisted pair operation: Please connect to GND directly or through a resistor. Fiber operation: Please connect to the fiber transceiver signal detect output pin. TEST0 I5/S 47 Test pin.
17、For normal operation, user should connect to ground. TEST1 I5/S 46 Test pin. For normal operation, user should connect to ground. X1 I3 62 Test pin. For normal operation, user should connect to ground. X2 O3 61 Test pin. No connection TCLK_EN I5/PD/S 43 Test pin. For normal operation, user should ke
18、ep this pin NC. TCLK_0 I5/PD 42 Test pin. For normal operation, user should keep this pin NC. TCLK_1 I5/PD 41 Test pin. For normal operation, user should keep this pin NC. On-chip Regulator Pins VCC3R3 P 52 3.3V Power supply to on-chip 3.3V to 1.8V voltage regulator. GND3R3 P 53 Ground pin of on-chi
19、p 3.3V to 1.8V voltage regulator. V18F P 51 1.8V voltage output of on-chip 3.3V to 1.8V voltage regulator. Power and Ground Pins VCCK P 20, 24, 36, 49 Digital Core Power. 1.8V. VCC3IO P 16, 44 Digital I/O Power. 3.3V. GND P 15, 22, 37, 48 Digital Ground. VCC33A_H P 60 Analog Power for USB transceive
20、r. 3.3V. GND33A_H P 55 Analog Ground for USB transceiver. VCC33A_PLL P 59 Analog Power for USB PLL. 3.3V. GND33A_PLL P 54 Analog Ground for USB PLL. VCC3A3 P 6 Analog Power for Ethernet PHY bandgap. 3.3V. VCC18A P 1, 11 Analog Power for Ethernet PHY and 25Mhz crystal oscillator. 1.8V. GND18A P 4, 8,
21、 14 Analog Ground for Ethernet PHY and 25Mhz crystal oscillator. VCC18A_PLL P 64 Analog Power for USB PLL. 1.8V. GND18A_PLL P 63 Analog Ground for USB PLL. Table 1 : AX88772B Pinout Description 15AX88772BLF / AX88772BLI Low-power USB 2.0 to 10/100M Fast Ethernet ControllerCopyright 2010-2010 ASIX El
22、ectronics Corporation. All rights reserved. 2.2 Hardware Setting For Operation Mode and Multi-Function Pins The following hardware settings define the desired function or interface modes of operation for some multi-function pins. The logic level shown on setting pin below is loaded from the chip I/O
23、 pins during power on reset based on the setting of the pins pulled-up (as logic 1) or pulled-down (as logic 0) resister on the schematic. z Chip Operation Mode setting : Pin# 19, Pin #21 Operation Modes Remarks 1x (default) MAC mode Internal PHY The Chip Operation Mode is determined by Pin# 19 (MFA
24、2/RMII_N) and Pin #21 (MFA3/PHY_N) value of AX88772B, which is called hardware setting. 01 MAC mode RMII00 PHY mode Reverse-RMII z EECK pin: USB force to Full Speed mode : EECK Description 0 Normal operation (default). 1 USB force to Full Speed mode. External pull-up resistor must be 4.7Kohm. z GPIO
25、_1 pin: Determines whether this chip will go to Default WOL Ready Mode after power on reset. The WOL stands for Wake-On-LAN. GPIO_1 Description 0 Normal operation mode (default, see Note 1). 1 Enable Default WOL Ready Mode. Notice that the external pulled-up resistor must be 4.7Kohm. For more detail
26、s, please refer to APPENDIX A. Default Wake-On-LAN (WOL) Ready Mode Note 1: This is the default with internal pulled-down resistor and doesnt need an external one. z EEPROM Flag 12: Defines the multi-function pin GPIO_0 / PME GPIO_0 is a general purpose I/O normally controlled by vendor commands. Us
27、ers can change this pin to operate as a PME (Power Management Event) for remote wake up purpose. Please refer to 4.1.2 Flag of bit 12 (PME_PIN). z MFA_3 MFA_0 pins: There are 4 multi-function pins for LED display purpose and as GPIO control by vendor command. Table 2 : MFA_3 MFA_0 pin configuration
28、PIN Name Default definition Vendor Command LED_MUX Vendor Command VMFAIO RMII_N enable MFA3 LED_USB indicater Sel_LED3 MFAIO_3 - MFA2 LED_Ethernet_LINK_Active Sel_LED2 MFAIO_2 - MFA1 LED_Ethernet_Speed Sel_LED1 MFAIO_1 MDIO MFA0 LED_Ethernet_Duplex_Collision Sel_LED0 MFAIO_0 MDC 16AX88772BLF / AX887
29、72BLI Low-power USB 2.0 to 10/100M Fast Ethernet ControllerCopyright 2010-2010 ASIX Electronics Corporation. All rights reserved. z PIN configuration of MFA and MFB Pin# 19 MFA2/RMII_N Pin #21 MFA3/PHY_N Description 1: MFB7MFB0 0: RMII 1: MAC Mode 0: PHY Mode PIN Name Function Pin Type 1 X MFB0 MFBI
30、O0 Bidirection, controlled by MFBIOEN0 1 X MFB1 MFBIO1 Bidirection, controlled by MFBIOEN1 1 X MFB2 MFBIO2 Bidirection, controlled by MFBIOEN2 1 X MFB3 MFBIO3 Bidirection, controlled by MFBIOEN3 1 X MFB4 MFBIO4 Bidirection, controlled by MFBIOEN4 1 X MFB5 MFBIO5 Bidirection, controlled by MFBIOEN5 1
31、 X MFB6 MFBIO6 Bidirection, controlled by MFBIOEN6 1 X MFB7 MFBIO7 Bidirection, controlled by MFBIOEN7 1 X MFA0 Refer to MFA Configuration 1 X MFA1 Refer to MFA Configuration 1 X MFA2 Refer to MFA Configuration 1 X MFA3 Refer to MFA Configuration 0 1 MFB0 MFBIO0 Bidirection, controlled by MFBIOEN0 0
32、 1 MFB1 CRSDV Input 0 1 MFB2 TXEN Output 0 1 MFB3 TXD1 Output 0 1 MFB4 TXD0 Output 0 1 MFB5 REF50 Input/Output control by EEPROM flag1 0 1 MFB6 RXD1 Input 0 1 MFB7 RXD0 Input 0 1 MFA0 MDC Output 0 1 MFA1 MDIO I/O 0 0 MFB0 MFBIO0 Bidirection, controlled by MFBIOEN0 0 0 MFB1 TXEN Input MFB2 CRSDV Outp
33、ut 0 0 MFB3 RXD1 Output 0 0 MFB4 RXD0 Output 0 0 MFB5 REF50 Input/Output control by EEPROM flag1 0 0 MFB6 TXD1 Input 0 0 MFB7 TXD0 Input MFA0 MDC Input 0 0 MFA1 MDIO I/O 17AX88772BLF / AX88772BLI Low-power USB 2.0 to 10/100M Fast Ethernet ControllerCopyright 2010-2010 ASIX Electronics Corporation. A
34、ll rights reserved. 3 Function Description 3.1 USB Core and Interface The USB core and interface contains a USB 2.0 transceiver, serial interface engine (SIE), USB bus protocol handshaking block, USB standard command, vendor command registers, logic for supporting bulk transfer, and an interrupt tra
35、nsfer, etc. The USB interface is used to communicate with a USB host controller and is compliant with USB specification V1.1 and V2.0. 3.2 10/100M Ethernet PHY The 10/100M Fast Ethernet PHY is compliant with IEEE 802.3 and IEEE 802.3u standards. It contains an on-chip crystal oscillator, PLL-based c
36、lock multiplier, and a digital phase-locked loop for data/timing recovery. It provides over-sampling mixed-signal transmit drivers compliant with 10/100BASE-TX transmit wave shaping / slew rate control requirements. It has a robust mixed-signal loop adaptive equalizer for receiving signal recovery.
37、It contains a baseline wander corrective block to compensate data dependent offset due to AC coupling transformers. It supports auto-negotiation and auto-MDIX functions. 3.3 MAC Core The MAC core supports 802.3 and 802.3u MAC sub-layer functions, such as basic MAC frame receive and transmit, CRC che
38、cking and generation, filtering, forwarding, flow-control in full-duplex mode, and collision-detection and handling in half-duplex mode, etc. It provides a reduce-media-independent interface (RMII) for implementing Fast Ethernet and HomePNA functions. The MAC core interfaces to external RMII/Reverse
39、-RMII interfaces and the embedded 10/100M Ethernet PHY. The selection among the interfaces is done via setting Pin# 19 (MFA2/RMII_N) and Pin #21 (MFA3/PHY_N) of AX88772B package pinout during power on reset (see 2.2) and using the USB vendor command, Software Interface Selection register. Figure 8 s
40、hows the data path diagram of 10/100M Ethernet PHY and RMII/Reverse-RMII interfaces to MAC core. Figure 8 : Internal Data path Diagram of 10/100M Ethernet PHY and RMII/Reverse-RMII Interfaces MAC Core 10/100 Ethernet PHY RXTXREFCLK, RXD 1:0, CRSDV, TXD 1:0, TXEN RXIP/RXIN TXOP/TXON RMII/Reverse-RMII
41、 18AX88772BLF / AX88772BLI Low-power USB 2.0 to 10/100M Fast Ethernet ControllerCopyright 2010-2010 ASIX Electronics Corporation. All rights reserved. 3.4 Checksum Offload Engine (COE) The Checksum Offload Engine (COE) supports IPv4, IPv6, layer 4 (TCP, UDP, ICMP, ICMPv6 and IGMP) header processing
42、functions and real time checksum calculation in hardware The COE supports the following features in layer 3: z IP header parsing, including IPv4 and IPv6 z IPv6 routing header type 0 supported z IPv6 in IPv4 tunnel supported z IPv4 header checksum check and generation (There is no checksum field in
43、IPv6 header) z Version error detecting on RX direction for IP packets with version != 4 or 6 z Detecting on RX direction for IP packets with error header checksum The COE supports the following features in layer 4: z TCP and UDP checksum check and generation for non-fragmented packet z ICMP, ICMPv6
44、and IGMP message checksum check and generation for non-fragmented packet z Packet filtering or checksum error indication on RX direction for TCP/UDP/ICMP/ICMPv6/IGMP packets with error checksum 3.5 Operation Mode For simple USB 2.0 to Ethernet applications, user can use the AX88772B, which operates
45、with internal Ethernet PHY. AX88772B supports following three operation modes: (Ref. 2.2 Hardware Setting For Operation Mode And Multi-Function Pins) 1. MAC mode 2. PHY mode Below provides a detailed description for the three operation modes: z In MAC mode, the AX88772B Ethernet block is configured
46、as an Ethernet MAC. From a system application standpoint, AX88772B can be used as a USB 2.0 to LAN Adaptor (see Figure 2) or a USB 2.0 to Fast Ethernet and HomePNA Combo (see Figure 3). In MAC mode, the AX88772B internal datapath can work with internal Ethernet PHY or RMII interface by setting Softw
47、are Interface Selection register. Note that the PHY_ID for the internal Ethernet PHY and external one are defined in below Table 3. Please refer to below Figure 9, Figure 10 for RMII example. z In PHY mode, the AX88772B Ethernet block is configured as an Ethernet PHY interface. In this case, an exte
48、rnal microcontroller with Ethernet MAC can interface with AX88772B as if it were to interface with an Ethernet PHY chip, and AX88772B can act as a USB to Reverse-RMII bridge chip for the microcontroller to provide USB 2.0 device interface for some system applications (see Figure 4). Please refer to
49、below Figure 11, Figure 12 for Reverse-RMII example. STA PHY_ID MAC mode PHY mode Embedded Ethernet PHY PHY_ID 4:0 10h 10h External Media Interface PHY_ID 4:0 Secondary PHY_ID 4:0 Secondary PHY_ID 4:1, 0 Note: The value of Secondary PHY_ID 4:0 is defined in EEPROM memory map 4.1.6 Table 3 : AX88772B PHY_ID Definition Source 19AX88772BLF / AX88772BLI Low-power USB 2.0 to 10/100M Fast Ethernet ControllerCopyright 2010-2010 ASIX Electronics Corporation. All rights
