1、信息工程专业英语题目：未来宽带网络的高性能住宅网关学 院：信息工程班 级：信工 131（通信）姓 名：郑浩学 号：20131524109指导老师：张树静时 间：2016-06-29High Performance Residential Gateway for Future Broadband NetworkAbstract-with development of broadband network and rich-content services from Internet, a high performance residential gateway is required in hom
2、e network. In the paper, a residential gateway (RG) is presented based on multi-core network processor and media processor. The expansibility of RG hardware is described through hardware architecture. And it outlines the architecture of RG software, which supports multi-core and multi-processor hard
3、ware. In QoS of RG，queue control and session handoff are considered. The RG will support future broadband network.Keywords-Home Network; Residential Gateway(RG); Quality of Service(QoS); Information Service; Multi-core ProcessorI. INTRODUCTIONAs development of broadband network and rich-content serv
4、ices from Internet, a high performance residential gateway is required in home network. Now, most of Internet conceptions focus on speedy network, colorful services, high performance and low cost. Many services, such as online game, Internet-TV, VoIP and VoD (Video on Demand), require network from r
5、eal-time, fitter and package loss rate. A high performance residential gateway is required in home network. Comparing with other equipments of network, generally, Residential Gateway (RG) is an embedded system and has a lower hardware level. So RG becomes an important footing of multi-services netwo
6、rk, such as telecommunication networks, TV networks and computer networks (Internet). And thin terminal impression of RG will being changed.For high performance convergence networks, RG must be available, secure, manageable and accountable. Achieve these objectives, a residential gateway (RG) is pre
7、sented based on multi-core network processor and media processor in the pape, including application scenario in section II, hardware architecture in section III, software architecture in section IV and QoS thinking in section V.II. APPLICATION SCENARIOThe application scenario of RG is shown in Figur
8、e 1. RG is a gateway between home network and extenal network, such as telecommunication networks, TV networks and computer networks (Internet). Though RG, wire network and wireless network is built in home network, i.e. 802.11a/b/g wireless network and 10/100/1000Base LAN. Many home facilities, suc
9、h as IP STB, computer, and laptop, can connect to the LAN through wireless or wire mode. Furthermore, multi-interfaces supports automation equipment，store device, digital camera, TV and telephone.Based on the scenario, RG need support services from telecommunication networks, TV networks and compute
10、r networks (Internet), which requires many interface modes and processing capabilities. In interface modes, it should have optical fiber, coaxial cable, telephone line and so on. In processing capabilities, it should have functions of protocol adaptation, data encapsulation and data Syntax.On other
11、hand, adapting to requirement of commercial network, RG support many key items: Security Scheme, QoS Requirement, Manageable and Accountable Scheme.Firewall based NAT technology is an important guard. Many classes of service traffic, WWW, VoIP, Video and FTP etc., converge on RG. RG must process or
12、forward them. Considering CPUs process capability and hardware resource, such CPU mips, memory capability and forward efficiency and so on. QoS control may be hard and ingenious. QoS scheme must be simply and availably implemented. A simple DiffServ1 algorithm is placed on RG.At the management respe
13、ct, RG has local or remote management functions through Web and telenet. Many functions and options are configured by them. And service provider easily carries through software updates and new services deployment. RG have a maturity database for detail tolling entries.III. HARDWARE ARCHITECTURERG ma
14、inly consists of four modules or parts, which are NPP (Network Processing Part), Media Process Part (MPP), NAM( Network Access Module) and NPM(Normal Periphery Module). Figure 2 shows the hardware architecture of RG.RG has two main parts: NPP is mainly based on multi- core processor and MPP is mainl
15、y based on media processor. Main chip of NPP is CN3860 coming from Cavium corporation. CN3860 is Multi-core MIPS64 processors, which targets intelligent, multi-gigabit networking, control plane, storage, and wireless applications in next-generation equipment. The family includes fifteen software-com
16、patible processors, with four to sixteen cnMIPS64 cores on a single chip that integrate next-generation networking I/Os along with the most advanced security and application hardware acceleration2.Main chip of NPP is SMP8670 coming from Sigma Designs corporation. The SMP8670 provides a highly-integr
17、ated and high-performance solution for media processing. The Secure Media Processor architecture offers advanced content protection, supporting a wide variety of Digital Rights Management (DRM) and Conditional Access (CA) solutions3. NAM supports interfaces of fiber, coaxial cable, telephone line. N
18、PM supports interfaces of SATA, DART, USB, DDR Memory and Flash Memory. IV. SOFTWARE ARCHITECTURERG has five modules: RTOS(Real Time Operating System )module, Network Module, BSP(Board Support Package) Driver module, MPEG Decode and VoIP module. Figure 3 shows the software architecture of RG.RTOS mo
19、dule has topmost control power of system resources, including hardware and software. System tasks control show RTOS power. Bus control, Memory control, TCP/IP stack, multi-services schedule is implemented on the module. Other modules communicate with the module through the event scheme.BSP Driver Mo
20、dule provide an interface to hardware components of NAM and NPM, i.e. Cable Tuner, Switch ,ADSL2+ PHY and other chips driver. The drivers allow the upper RTOS or applications to control hardware components.Network module contains WAN Control, LAN Control and 802.11b Control. The WAN interface ADSL2+
21、 and Ethernet. But the system mainly uses ADSL2+ as Internet access mode. LAN Control is wire VLAN (Virtual Lan) management. 802.11b Control implements wireless LAN management and WEP.MPEG Decode Module supports MPEG 1/2/4 Decode, mainly including Interface Driver and A/V Manager. A/V Manager fulfil
22、ls MPEG Decode, containing data buffer and traffic control schemes to assure QoS. Interface Driver are for IDE and USB, which supply media recording and favorite information store.VoIP Module contains Phone Interface, Signaling Control and Voice Data Control. Phone Interface provides software compo-
23、 nents that handle interface between user and ADSL2+ PHY. It implements Hook Off/On signaling handle, Tone On/Off, DTMF digits send-out and voice compression/decompression configure. The protocols, such as H.323, SIP and MGCP/H.248, are completely set on the system. Voice Stream Control mainly conta
24、ins voice compression/decompression data buffer management and voice stream control through RTP and RTCP.Application Module is composed of Firewall, SNMP, QoS Manager and TFTP. Firewall with NAT provide the system security. SNMP gives a management function for MIBs(Management Information Bases). TFT
25、P (Trivial File Transport Protocol) client is used to download upgrade or update files.CN3860 is based on multi-core and collaborative work and shared memory management, drivers, as shown in Figure 4. Discussed in more detail below shared memory management, registration and multi-function table func
26、tion- calls between the CPU and other modules to achieve.Multi-core shared memory board, although some memory is used exclusively by a single CPU; virtually all of the available memory is shared memory, as shown below:(1) Some memory is given the exclusive use of CPU, which stores appropriate operat
27、ing system and procedures;(2) Some memory is shared memory, to facilitate communication between CPU and provide data pipe and up the function table.And Multi-core system efficiency is closely related to the latter. The following paper discusses the main focus on the latter.Multi-core shared memory i
28、s used by the public storage. In start-up phase, it is initialized 饰 the CPUO. Through the submission of memory identity and size, any CPU applies for shared memory. Additional CPU can use the same memory area using identity. Probably all the CPU may also use the same memory, so both read and write
29、are protected by hardware signals to avoid multi-core simultaneous access to shared memory. In addition, based on the shared memory of data path, the CPU can save memory and reduce memory copy, which effectively improves the efficiency of embedded systems.Shared memory up function table is for remot
30、e calls between multiple cores to provide client/server (C/S: Client /Server) call model. C/S mode realization described as follows: CPUj with realization and implementation of the function is a server, whose CPU-ID and the specific function are registered the registration function and function poin
31、ter entry in the table. CPUi which calls the function is a client, through the registration function table to call function. Client applications can be retrieved by the function name to achieve the CPU ID function and its implementation functions. With CPUj data pipeline, parameters can been passed
32、to CPUjIf the called function has the results back to the CPUi, they can be passed back using CPUi data pipeline. Functions registered on the server has an indirect blocking mode and indirect non-blocking mode. In the indirect blocking mode, the client need to get return values from the server, that
33、 is, the caller must wait until the process is finished. Before performing this function, the caller is blocked. The configuration function with the return value is called as indirect block function. In indirect non-blocking mode, client calls the server, which does not need to obtain the return val
34、ue.CPUO is registered in the function table Demo()function, so CPUO a server, Multi-core provides the printf()service. Allocated from the function table Demo()，CPU 1 indirectly called Demo()function, which as a client.When the server performs the function, if the function call on CPUO function modul
35、es, such as printf()function, the corresponding characters will be displayed on the console output, called an indirect non-blocking calls. If you need to perform a function with return value, CPU 1 Data access will be through the return value to return, and CPU1 need to wait for the return value, ca
36、lled the indirect blocking call.Multi-core communication signals between the memory sharing mechanism is an important foundation for achieving the main way to achieve this through an interrupt mechanism to ensure real-time information and data exchange requirements, which is referred to as the proce
37、ssor to the processor interrupt (PTP: Processor-to -Processor) interrupt. PTP CPU interrupt occurs between the source and target CPU, in which the purpose are:(1) The source and target CPUs, can use the CPU data path (shared memory) to exchange data, reducing memory copies and improving the efficien
38、cy of the system, especiallythe large quantities of network data, such as the exchange between CPUO and CPU1 Network packets, CPU2 and CPU1 exchange between the real-time voice data.(2) to achieve that the target CPU executes the function which the source CPU calls, which achieves parallel processin
39、g system CPU, which greatly improves system efficiency.V. QOS THINKINGQoS thinking should be systemic and detailed. From protocol layers, QoS control focuses on the IP layer, which does justice to TCP and UDP data. For the stream QoS trait, QoS thinking brandwith, fitter, data duration, data quantit
40、y ,delay, client sensitivity of QoS, etc. Simple WFQ56(Weight Fair Queueing) algorithm is implemented on the system, including two stages. First stage, multi-services start-up, the service priority (weight) is fixed. The Order of priority is Voice data, A/V data and other data service from higher to
41、 lower level. Second stage, multi- services full-work, the service priority (weight) is self- adaptive, thinking over occupancy buffer quantity, real-time trait, burst data quantity and burst period. Through NS2 simulation, the system shows preferable QoS property.Session handoff control module incl
42、uding information collector, arbiter, session trigger and handoff task manager, as shown in Figure 5.Information collector is responsible for sharing information collection, which polls session handoff-related information, such information includes network information, user information and sensor in
43、formation. RG and WLAN network information is the connection between the state, performance and the current session of the network connection, such as WLAN or GPRS. User information is user set handoff threshold, the priority of access networks and so on. Sensor information is the use of position se
44、nsor information as a condition of the trigger switch (extended support).The arbiter is responsible for the information providing under the Information collector, weigh the user settings, network performance and service quality, the formation of arbitration whether to switch, switch mode (handoff is
45、 GPRS or WLAN to GPRS to WLAN handoff).Trigger responsible for the arbitration session, the result of the formation of the instruction sessions, instructions to handoff UA(User Agent) moves into the switching process. Handoff Task Manager - Control Module as the core handoff control to ensure the in
46、formation collector, arbiter and session trigger work together. VI. CONCLUSIONThe paper presents the design and analysis of Residential Gateway. It supplies a total solution to the digital home network. For detail security, management and QoS thinking, RG can be adapted Future Broadband Network.REFE
47、RENCES1IETF working group on DifferentiateService.http:/www.iet#org/html.charters/diffserv-charter.html2Cavium Network OCTEON CN38XX Hardware Reference Manual,http:/ CN38XX CN36XX.ht ml3Sigma Designs SMP8670 Datasheet,http:/ _processor_overview.php4A.K. Parekh and R.G. Gallager. A gene-ralized proce
48、ssor sharing approach to flow control in integrated services networks: The multiple node case. IEEE/ACM Transactions on the Networking, Vo1.2,No.2,pp:137150, Apr.19945Barry Luong, Evaluation Modeling In Performance and Resource Allocation for Restidential Broadband Gatways,Califomia State University
49、,Long Beach,2003未来宽带网络的高性能住宅网关摘要：随着宽带网络的发展和互联网上丰富的内容服务，家庭网络需要一个高性能的住宅网关。在本文中，住宅网关（RG）是基于多核网络处理器和媒体处理器介绍。RG 硬件的可扩展性是通过硬件体系结构描述。它概述了该软件的体系结构，它支持多核多处理器硬件。在 QoS 的 RG，考虑队列控制和会话切换。RG 将支持未来的宽带网络。关键词家庭网络；住宅网关（ RG） ；服务质量（ QoS） ；信息服务；多核心处理器一、引言随着宽带网络的发展和互联网上丰富的内容服务，家庭网络需要一个高性能的住宅网关。现在，大多数互联网概念专注于快速的网络，丰富多彩的服务，高性能和低成本。许多服务，如在线游戏、网络电视、VOIP 和 VOD（视频点播） ，要求网络的实时、钳工和包丢失率。家庭网络中需要一个高性能的住宅网关。与网络中的其他设备，一般来说，住宅网关（RG）是一个嵌入式系统具有较低的硬件水平。所以 RG 成为多服务网络的重要基础，如电信网、电视网和计算机网（互联网） 。和 RG 瘦终端的印象将被改变。对于高性
