1、TMS320VC5416Fixed-Point Digital Signal ProcessorData ManualLiterature Number: SPRS095OMarch 1999 Revised January 2005PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does no
2、tnecessarily include testing of all parameters.Revision HistoryTMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095O MARCH 1999 REVISED JANUARY 2005This data sheet revision history highlights the technical changes made to the SPRS095N device-specificdata sheet to make it an SPRS095O revision.Scop
3、e: This document has been reviewed for technical accuracy; the technical content is up-to-date as ofthe specified release date with the following corrections.SECTION ADDITIONS/CHANGES/DELETIONSSection 5.2 Changed I OH from -2 to -8 mA and I OL from 2 to 8 mA. Changed Note 2 to read “These output cur
4、rent limits areused for the test conditions on V OL and V OH , except where noted otherwise.“Chapter 6 Removed Section 6.2 to prevent duplication of Product Information.Revision HContentsTMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095O MARCH 1999 REVISED JANUARY 2005Revision History . 21 TMS
5、320VC5416 Features . 92 Introduction . 102.1 Description 102.2 Pin Assignments 102.2.1 Terminal Assignments for the GGU Package . 102.2.2 Pin Assignments for the PGE Package 122.2.3 Signal Descriptions 133 Functional Overview . 163.1 Memory 163.1.1 Data Memory . 163.1.2 Program Memory 183.1.3 Extend
6、ed Program Memory . 183.2 On-Chip ROM With Bootloader . 183.3 On-Chip RAM . 193.4 On-Chip Memory Security . 193.5 Memory Map 203.5.1 Relocatable Interrupt Vector Table 213.6 On-Chip Peripherals . 233.6.1 Software-Programmable Wait-State Generator . 233.6.2 Programmable Bank-Switching 253.6.3 Bus Hol
7、ders 263.7 Parallel I/O Ports . 263.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16) 273.7.2 HPI Nonmultiplexed Mode 283.8 Multichannel Buffered Serial Ports (McBSPs) 303.9 Hardware Timer 323.10 Clock Generator 323.11 Enhanced External Parallel Interface (XIO2) . 343.12 DMA Controller . 373.12.1
8、 Features 373.12.2 DMA External Access . 373.12.3 DMA Memory Maps . 393.12.4 DMA Priority Level . 403.12.5 DMA Source/Destination Address Modification . 403.12.6 DMA in Autoinitialization Mode 413.12.7 DMA Transfer Counting . 413.12.8 DMA Transfer in Doubleword Mode 423.12.9 DMA Channel Index Regist
9、ers . 423.12.10 DMA Interrupts 423.12.11 DMA Controller Synchronization Events 423.13 General-Purpose I/O Pins . 433.13.1 McBSP Pins as General-Purpose I/O . 433.13.2 HPI Data Pins as General-Purpose I/O 443.14 Device ID Register . 443.15 Memory-Mapped Registers . 453.16 McBSP Control Registers and
10、Subaddresses 473.17 DMA Subbank Addressed Registers 483.18 Interrupts 50Contents TMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095O MARCH 1999 REVISED JANUARY 20054 Support . 514.1 Documentation Support . 514.2 Device and Development-Support Tool Nomenclature 525 Electrical Specifications 535.
11、1 Absolute Maximum Ratings . 535.2 Recommended Operating Conditions . 535.3 Electrical Characteristics . 545.3.1 Test Loading . 545.3.2 Timing Parameter Symbology 555.3.3 Internal Oscillator With External Crystal . 565.4 Clock Options . 575.4.1 Divide-By-Two and Divide-By-Four Clock Options 575.4.2
12、Multiply-By-N Clock Option (PLL Enabled) . 595.5 Memory and Parallel I/O Interface Timing 605.5.1 Memory Read 605.5.2 Memory Write 635.5.3 I/O Read 645.5.4 I/O Write 655.5.5 Ready Timing for Externally Generated Wait States 675.5.6 HOLD and HOLDA Timings . 725.5.7 Reset, BIO , Interrupt, and MP/ MC
13、Timings . 745.5.8 Instruction Acquisition ( IAQ ) and Interrupt Acknowledge ( IACK ) Timings 765.5.9 External Flag (XF) and TOUT Timings 775.5.10 Multichannel Buffered Serial Port (McBSP) Timing 785.5.10.1 McBSP Transmit and Receive Timings 785.5.10.2 McBSP General-Purpose I/O Timing 815.5.10.3 McBS
14、P as SPI Master or Slave Timing 825.5.11 Host-Port Interface Timing . 865.5.11.1 HPI8 Mode . 865.5.11.2 HPI16 Mode . 906 Mechanical Data . 936.1 Package Thermal Resistance Characteristics 934 CTMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095O MARCH 1999 REVISED JANUARY 2005List of Figures2-1
15、144-Ball GGU MicroStar BGA (Bottom View) . 102-2 144-Pin PGE Low-Profile Quad Flatpack (Top View) . 123-1 TMS320VC5416 Functional Block Diagram 163-2 Program and Data Memory Map 203-3 Extended Program Memory Map . 213-4 Process Mode Status Register 223-5 Software Wait-State Register (SWWSR) Memory-M
16、apped Register (MMR) Address 0028h . 233-6 Software Wait-State Register (SWWSR) Memory-Mapped Register (MMR) Address 0028h . 243-7 Bank-Switching Control Register BSCR)MMR Address 0029h . 253-8 Host-Port Interface Nonmulltiplexed Mode . 283-9 HPI Memory Map . 293-10 Multichannel Control Register (MC
17、R1) . 313-11 Multichannel Control Register (MCR2) . 313-12 Pin Control Register (PCR) 323-13 Nonconsecutive Memory Read and I/O Read Bus Sequence . 343-14 Consecutive Memory Read Bus Sequence (n = 3 reads) 353-15 Memory Write and I/O Write Bus Sequence . 363-16 DMA Transfer Mode Control Register (DM
18、MCRn) . 373-17 On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0) . 393-18 On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0) 403-19 DMPREC Register 413-20 General-Purpose I/O Control Register (GPIOCR) MMR Address 003Ch 443-21 General-Purpose I/O Status Register (
19、GPIOSR) MMR Address 003Dh . 443-22 Device ID Register (CSIDR) MMR Address 003Eh . 443-23 IFR and IMR Registers . 505-1 Tester Pin Electronics 545-2 Internal Divide-By-Two Clock Option With External Crystal . 565-3 External Divide-By-Two Clock Timing . 585-4 Multiply-By-One Clock Timing 595-5 Noncons
20、ecutive Mode Memory Reads . 615-6 Consecutive Mode Memory Reads 625-7 Memory Write ( MSTRB = 0) 635-8 Parallel I/O Port Read ( IOSTRB = 0) . 655-9 Parallel I/O Port Write ( IOSTRB = 0) 665-10 Memory Read With Externally Generated Wait States . 685-11 Memory Write With Externally Generated Wait State
21、s . 695-12 I/O Read With Externally Generated Wait States . 705-13 I/O Write With Externally Generated Wait States . 715-14 HOLD and HOLDA Timings (HM = 1) . 73List of Figures TMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095O MARCH 1999 REVISED JANUARY 20055-15 Reset and BIO Timings . 745-16
22、Interrupt Timing 755-17 MP/ MC Timing . 755-18 Instruction Acquisition ( IAQ ) and Interrupt Acknowledge ( IACK ) Timings 765-19 External Flag (XF) Timing 775-20 TOUT Timing . 775-21 McBSP Receive Timings . 795-22 McBSP Transmit Timings . 805-23 McBSP General-Purpose I/O Timings 815-24 McBSP Timing
23、as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 825-25 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 835-26 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 845-27 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 855-28 Using HDS to Control Accesses ( HCS Alway
24、s Low) 885-29 Using HCS to Control Accesses . 895-30 HINT Timing 895-31 GPIOx Timings . 895-32 Nonmultiplexed Read Timings . 915-33 Nonmultiplexed Write Timings . 925-34 HRDY Relative to CLKOUT 926 List of FTMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095O MARCH 1999 REVISED JANUARY 2005List
25、of Tables2-1 Terminal Assignments for the TMS320VC5416GGU (144-Pin BGA Package) . 112-2 Signal Descriptions . 133-1 Standard On-Chip ROM Layout . 193-2 Processor Mode Status (PMST) Register Bit Fields 223-3 Software Wait-State Register (SWWSR) Bit Fields . 243-4 Software Wait-State Control Register
26、(SWCR) Bit Fields 243-5 Bank-Switching Control Register (BSCR) Fields 253-6 Bus Holder Control Bits 263-7 Sample Rate Input Clock Selection . 323-8 Clock Mode Settings at Reset . 333-9 DMD Section of the DMMCRn Register 383-10 DMA Reload Register Selection . 413-11 DMA Interrupts . 423-12 DMA Synchr
27、onization Events 423-13 DMA Channel Interrupt Selection 433-14 Device ID Register (CSIDR) Bits 453-15 CPU Memory-Mapped Registers 453-16 Peripheral Memory-Mapped Registers for Each DSP Subsystem 463-17 McBSP Control Registers and Subaddresses . 473-18 DMA Subbank Addressed Registers . 483-19 Interru
28、pt Locations and Priorities 505-1 Input Clock Frequency Characteristics . 565-2 Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options . 575-3 Divide-By-2 and Divide-By-4 Clock Options Timing Requirements . 575-4 Divide-By-2 and Divide-By-4 Clock Options Switching Characteristi
29、cs . 575-5 Multiply-By-N Clock Option Timing Requirements 595-6 Multiply-By-N Clock Option Switching Characteristics 595-7 Memory Read Timing Requirements 605-8 Memory Read Switching Characteristics . 605-9 Memory Write Switching Characteristics . 635-10 I/O Read Timing Requirements 645-11 I/O Read
30、Switching Characteristics . 645-12 I/O Write Switching Characteristics 655-13 Ready Timing Requirements for Externally Generated Wait States 675-14 Ready Switching Characteristics for Externally Generated Wait States 675-15 HOLD and HOLDA Timing Requirements 725-16 HOLD and HOLDA Switching Character
31、istics . 725-17 Reset, BIO , Interrupt, and MP/ MC Timing Requirements 745-18 Instruction Acquisition ( IAQ ) and Interrupt Acknowledge ( IACK ) Switching Characteristics . 76List of Tables TMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095O MARCH 1999 REVISED JANUARY 20055-19 External Flag (XF
32、) and TOUT Switching Characteristics . 775-20 McBSP Transmit and Receive Timing Requirements . 785-21 McBSP Transmit and Receive Switching Characteristics 795-22 McBSP General-Purpose I/O Timing Requirements 815-23 McBSP General-Purpose I/O Switching Characteristics . 815-24 McBSP as SPI Master or S
33、lave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . 825-25 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . 825-26 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . 835-27 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 1
34、1b, CLKXP = 0) . 835-28 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . 845-29 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . 845-30 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . 855-31 McBSP as SPI Maste
35、r or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . 855-32 HPI8 Mode Timing Requirements . 865-33 HPI8 Mode Switching Characteristics 875-34 HPI16 Mode Timing Requirements 905-35 HPI16 Mode Switching Characteristics . 916-1 Thermal Resistance Characteristics 938 List of T1 TMS320VC5416
36、FeaturesTMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095O MARCH 1999 REVISED JANUARY 2005 Arithmetic Instructions With Parallel Store and Advanced Multibus Architecture With ThreeParallel LoadSeparate 16-Bit Data Memory Buses and OneProgram Memory Bus Conditional Store Instructions 40-Bit Ari
37、thmetic Logic Unit (ALU) Including a Fast Return From Interrupt40-Bit Barrel Shifter and Two Independent On-Chip Peripherals40-Bit Accumulators Software-Programmable Wait-State 17- 17-Bit Parallel Multiplier Coupled to a Generator and Programmable40-Bit Dedicated Adder for Non-Pipelined Bank-Switchi
38、ngSingle-Cycle Multiply/Accumulate (MAC) On-Chip Programmable Phase-LockedOperation Loop (PLL) Clock Generator With ExternalClock Source Compare, Select, and Store Unit (CSSU) for the One 16-Bit TimerAdd/Compare Selection of the Viterbi Operator Six-Channel Direct Memory Access (DMA) Exponent Encode
39、r to Compute an ExponentControllerValue of a 40-Bit Accumulator Value in a Three Multichannel Buffered Serial PortsSingle Cycle(McBSPs) Two Address Generators With Eight Auxiliary 8/16-Bit Enhanced Parallel Host-PortRegisters and Two Auxiliary RegisterInterface (HPI8/16)Arithmetic Units (ARAUs) Powe
40、r Consumption Control With IDLE1, Data Bus With a Bus Holder FeatureIDLE2, and IDLE3 Instructions With Extended Addressing Mode for 8M 16-BitPower-Down ModesMaximum Addressable External Program CLKOUT Off Control to Disable CLKOUTSpace On-Chip Scan-Based Emulation Logic, IEEE 128K x 16-Bit On-Chip R
41、AM Composed of:Std 1149.1 (JTAG) Boundary Scan Logic (1) Eight Blocks of 8K 16-Bit On-Chip 144-Pin Ball Grid Array (BGA)(GGU Suffix)Dual-Access Program/Data RAM 144-Pin Low-Profile Quad Flatpack Eight Blocks of 8K 16-Bit On-Chip(LQFP)(PGE Suffix)Single-Access Program RAM 6.25-ns Single-Cycle Fixed-P
42、oint Instruction 16K 16-Bit On-Chip ROM Configured forExecution Time (160 MIPS)Program Memory 8.33-ns Single-Cycle Fixed-Point Instruction Enhanced External Parallel Interface (XIO2)Execution Time (120 MIPS) Single-Instruction-Repeat and Block-Repeat 3.3-V I/O Supply Voltage (160 and 120 MIPS)Operat
43、ions for Program Code 1.6-V Core Supply Voltage (160 MIPS) Block-Memory-Move Instructions for BetterProgram and Data Management 1.5-V Core Supply Voltage (120 MIPS) Instructions With a 32-Bit Long Word Operand Instructions With Two- or Three-Operand (1) IEEE Standard 1149.1-1990 Standard-Test-Access
44、 Port andReads Boundary Scan ArchitectureTMS320C54x, TMS320 are trademarks of Texas Instruments.All trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date. Copyright 1999 2005, Texas Instruments IncorporatedProducts conform to specificati
45、ons per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all 2 Introduction2.1 Description2.2 Pin Assignments2.2.1 Terminal Assignments for the GGU PackageABDCEFHJLMKNG123456781012 1113 9TMS320VC5416Fixed-Point Digital Signal Processor
46、SPRS095O MARCH 1999 REVISED JANUARY 2005This section describes the main features of the TMS320VC5416, lists the pin assignments, and describesthe function of each pin. This data manual also provides a detailed description section, electricalspecifications, parameter measurement information, and mech
47、anical data about the available packaging.NOTEThis data manual is designed to be used in conjunction with the TMS320C54x DSPFunctional Overview (literature number SPRU307).The TMS320VC5416 fixed-point, digital signal processor (DSP) (hereafter referred to as the device unlessotherwise specified) is
48、based on an advanced modified Harvard architecture that has one programmemory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with ahigh degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chipperipherals. The basis of
49、 the operational flexibility and speed of this DSP is a highly specialized instructionset.Separate program and data spaces allow simultaneous access to program instructions and data, providinga high degree of parallelism. Two read operations and one write operation can be performed in a singlecycle. Instructions with parallel store and application-specific instructi
