1、MSP430F41x2MIXED SIGNAL MICROCONTROLLERSLAS648D - APRIL 2009 - REVISED SEPTEMBER 20101POST OFFICE BOX 655303DALLAS, TEXAS 75265D Low Supply-Voltage Range, 1.8 V to 3.6 VD Ultralow Power ConsumptionActive Mode: 220 Aat1MHz,2.2VStandby Mode: 0.9 AOff Mode (RAM Retention): 0.1 AD Five Power-Saving Mode
2、sD Wake-Up From Standby Mode in LessThan 6 s- Internal Very Low Power,Low-Frequency OscillatorD 16-Bit RISC Architecture,125-ns Instruction Cycle TimeD 16-Bit Timer_A With ThreeCapture/Compare RegistersD 16-Bit Timer_A With Five Capture/CompareRegistersD Two Universal Serial CommunicationInterfaces
3、(USCIs)USCI_A0- Enhanced UART SupportingAuto-Baudrate Detection- IrDA Encoder and Decoder- Synchronous SPIUSCI_B0- I2C- Synchronous SPID Supply Voltage Supervisor/Monitor WithProgrammable Level DetectionD Integrated LCD Driver With ContrastControl for Up to 144 SegmentsD Basic Timer With Real Time C
4、lock FeatureD Brownout detectorD On-Chip Comparator for Analog SignalCompare Function or Slope A/DD 10-Bit 200-ksps Analog-to-Digital (A/D)Converter With Internal Reference,Sample-and-Hold, Autoscan, and DataTransfer ControllerD Serial Onboard Programming,No External Programming Voltage NeededProgra
5、mmable Code Protection by SecurityFuseD Bootstrap LoaderD On-Chip Emulation ModuleD Family Members Include:MSP430F4152: 16KB+256B Flash Memory512B RAMMSP430F4132: 8KB+256B Flash Memory512B RAMD Available in 64-Pin QFP Package and48-Pin QFN Package (See AvailableOptions)D For Complete Module Descript
6、ions, SeeThe MSP430x4xx Family Users Guide,Literature Number SLAU056descriptionThe Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuringdifferent sets of peripherals targeted for various applications. The architecture, combined with five low powermod
7、es,isoptimizedtoachieveextendedbatterylifeinportablemeasurementapplications.Thedevicefeaturesa powerful 16-bit RISC CPU, 16-bit registers, and constant generator that contribute to maximum codeefficiency.Thedigitallycontrolledoscillator(DCO)allowswake-upfromlow-powermodestoactivemodeinlessthan 6 s.T
8、heMSP430F41x2isamicrocontrollerconfigurationwithtwo16-bittimers,abasictimerwithareal-timeclock,a 10-bit A/D converter, a versatile analog comparator, two universal serial communication interfaces, up to 48I/O pins, and a liquid crystal display driver.Typical applications for this device include anal
9、og and digital sensor systems, remote controls, thermostats,digital timers, hand-held meters, etc.This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescanc
10、ausedamage.ESDdamagecanrangefrom subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.Thesedeviceshavelimitedbuilt-in ESD protection.Please be
11、aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Copyright 2010, Texas Instruments IncorporatedPRODUCTION DATA information is current as
12、 of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.MSP430F41x2MIXED SIGNAL MICROCONTROLLERSLAS648D - APRIL 2009 - REVISED SEPTEMBER 20102 POST OFFICE BOX 655303DALLAS
13、, TEXAS 75265AVAILABLE OPTIONSTPACKAGED DEVICESAPLASTIC 64-PIN QFP (PM) PLASTIC 48-PIN QFN (RGZ)- 40Cto85CMSP430F4152IPMMSP430F4132IPMMSP430F4152IRGZMSP430F4132IRGZFor the most current package and ordering information, see the Package OptionAddendum at the end of this document, or see the TI web sit
14、e at .Package drawings, thermal data, and symbolization are available TOOL SUPPORTAll MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debuggingand programming through easy to use development tools. Recommended hardware options include thefollowing:D Debugging an
15、d Programming Interface- MSP-FET430UIF (USB)- MSP-FET430PIF (Parallel Port)D Debugging and Programming Interface with Target Board- MSP-FET430U64A (PM package)D Production Programmer- MSP-GANG430MSP430F41x2MIXED SIGNAL MICROCONTROLLERSLAS648D - APRIL 2009 - REVISED SEPTEMBER 20103POST OFFICE BOX 655
16、303DALLAS, TEXAS 75265pin designation, MSP430F41x2IPM (QFP)484764 63P6.1/UCB0SOMI/UCB0SCLP6.2/UCB0SIMO/UCB0SDAP6.3/UCB0STE/UCA0CLK/A3/CA5/VeREF-/VREF-XINXOUTP4.6/S1P4.5/S2P4.4/S3P4.3/S4P4.2/S5P4.1/S6P4.0/S7P2.7/S8P2.6/S9P2.5/S10P2.4/S11P2.3/TA1.4/S12P2.2/TA1.3/S13P2.1/TA1.2/S14P2.0/TA1.1/S15P3.7/S16
17、P3.6/S17P3.5/S18P3.4/CAOUT/S19P3.3/TA0.0/TA1CLK/S20P3.2/TA1.4/S21P5.7/COM0P5.6/COM1P5.5/COM2P5.4/COM3P5.3/R03P5.2/R13/LCDREFP5.1/R23R33/LCDCAPAVCCP6.0/TA1.2/A2/CA4P7.5/TA1.3/A1/CA3P7.4/TA1.4/A0/CA2RST/NMI/SBWTDIOP7.3/TCK/S35P7.2/TMS/S34P7.1/TDI/TCLK/S33P7.0/TDO/TDI/S32P1.0/TA0.0/S31P1.1/TA0.0/MCLK/S
18、3062 61 60 59 58 57 56 55 54 53 52 51 50 4946454443424140393837363534331234567891011121314151617 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32P3.1/TA1.3/S22P3.0/TA1.2/S23P5.0/TA1.1/S24P4.7/ADC10CLK/S0P1.4/TA1.0/S27P1.2/TA0.1/S29P1.3/TA1.0/SVSOUT/S28P6.4/UCB0CLK/UCA0STE/A4/CA6/VeREF+/VREF+P6.5/UCA0RXD
19、/UCA0SOMI/A564-pinPM PACKAGE(TOP VIEW)P6.7/A7/CA7/SVSINP7.6/TA0.2/S25TEST/SBWTCLKP6.6/UCA0TXD/UCA0SIMO/A6AVSSDVCCDVSSP1.7/TA0CLK/CAOUT/CA1P1.5/TA0CLK/CAOUT/S26P1.6/ACLK/CA0MSP430F41x2MIXED SIGNAL MICROCONTROLLERSLAS648D - APRIL 2009 - REVISED SEPTEMBER 20104 POST OFFICE BOX 655303DALLAS, TEXAS 75265
20、pin designation, MSP430F41x2IRGZ (QFN)XINXOUTP4.6/S1P4.5/S2P4.4/S3P4.3/S4P4.2/S5P4.1/S6P4.0/S7P2.7/S8P2.6/S9P2.5/S10P2.4/S11P2.3/TA1.4/S12P2.2/TA1.3/S13P2.1/TA1.2/S14P2.0/TA1.1/S15P5.7/COM0P5.6/COM1P5.5/COM2P5.4/COM3P5.3/R03P5.2/R13/LCDREFP5.1/R23R33/LCDCAPAVCCRST/NMI/SBWTDIOP4.7/ADC10CLK/S0TEST/SBW
21、TCLKAVSSDVCCDVSS48-pinRGZ PACKAGE(TOP VIEW)363548 47 46 45 44 43 42 41 40 39 38 373433323130292827262512345678910111213 14 15 16 17 18 19 20 21 22 23 24P6.0/TA1.2/A2/CA4P7.5/TA1.3/A1/CA3P7.4/TA1.4/A0/CA2P1.0/TA0.0/S31P1.7/TA0CLK/CAOUT/CA1P1.6/ACLK/CA0P6.1P6.2P6.7/A7/CA7/SVSINP7.3/TCK/S35P7.2/TMS/S34
22、P7.1/TDI/TCLK/S33P7.0/TDO/TDI/S32P3.4/CAOUT/S19P1.1/TA0.0/MCLK/S30P1.5/TA0CLK/CAOUT/S26“Not available” pins in the 48-pin package should be initialized to output direction.MSP430F41x2MIXED SIGNAL MICROCONTROLLERSLAS648D - APRIL 2009 - REVISED SEPTEMBER 20105POST OFFICE BOX 655303DALLAS, TEXAS 75265f
23、unctional block diagramOscillatorsFLL+VLOBrownoutProtectionSVS,SVMRST/NMIDVCC DVSSMCLKWatchdogWDT+15-BitTimer_A55CCRegistersCPU64kBincl. 16RegistersEEMJTAGInterfaceBasicTimer Table 2 shows the addressmodes.Table 1. Instruction Word FormatsDual operands, source-destination e.g., ADD R4,R5 R4+R5 -R5Si
24、ngle operands, destination only e.g., CALL R8 PC -(TOS), R8- PCRelative jump, un/conditional e.g., JNE Jump-on-equal bit = 0Table 2. Address Mode DescriptionsADDRESS MODE S D SYNTAX EXAMPLE OPERATIONRegister F F MOV Rs,Rd MOV R10,R11 R10 R11Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) M(6+R6)
25、Symbolic (PC relative) F F MOV EDE,TONI M(EDE) M(TONI)Absolute F F MOV&MEM,&TCDAT M(MEM) M(TCDAT)Indirect F MOV Rn,Y(Rm) MOV R10,Tab(R6) M(R10) M(Tab+R6)IndirectautoincrementF MOV Rn+,Rm MOV R10+,R11M(R10) R11R10+2R10Immediate F MOV #X,TONI MOV #45,TONI #45 M(TONI)NOTE: S = source, D = destinationMS
26、P430F41x2MIXED SIGNAL MICROCONTROLLERSLAS648D - APRIL 2009 - REVISED SEPTEMBER 201011POST OFFICE BOX 655303DALLAS, TEXAS 75265operating modesThe MSP430 has one active mode and five software selectable low-power modes of operation. An interruptevent can wake up the device from any of the five low-pow
27、er modes, service the request, and restore back tothe low-power mode on return from the interrupt program.The following six operating modes can be configured by software:D Active mode (AM)- All clocks are activeD Low-power mode 0 (LPM0)- CPU is disabled- ACLK and SMCLK remain active- FLL+ loop contr
28、ol remains activeD Low-power mode 1 (LPM1)- CPU is disabled- ACLK and SMCLK remain active- FLL+ loop control is disabledD Low-power mode 2 (LPM2)- CPU is disabled- MCLK, FLL+ loop control, and DCOCLK are disabled- DCOs dc generator remains enabled- ACLK remains activeD Low-power mode 3 (LPM3)- CPU i
29、s disabled- MCLK, FLL+ loop control, and DCOCLK are disabled- DCOs dc generator is disabled- ACLK remains activeD Low-power mode 4 (LPM4)- CPU is disabled- ACLK is disabled- MCLK, FLL+ loop control, and DCOCLK are disabled- DCOs dc generator is disabled- Crystal oscillator is stoppedMSP430F41x2MIXED
30、 SIGNAL MICROCONTROLLERSLAS648D - APRIL 2009 - REVISED SEPTEMBER 201012 POST OFFICE BOX 655303DALLAS, TEXAS 75265interrupt vector addressesThe interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0.The vector contains the 16-bit address of the appropria
31、te interrupt-handler instruction sequence.Iftheresetvector(locatedataddress0xFFFE)contains0xFFFF(e.g.,flashisnotprogrammed),theCPUgoesinto LPM4 immediately after power-up.INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPTWORDADDRESSPRIORITYPower-UpExternal ResetWatchdogFlash MemoryPC Out-of-Range (see
32、 Note 4)PORIFGRSTIFGWDTIFGKEYV(see Note 1)Reset 0xFFFE 15, highestNMIOscillator FaultFlash Memory Access ViolationNMIIFG (see Notes 1 and 3)OFIFG (see Notes 1 and 3)ACCVIFG (see Notes 1, 2, and 4)(Non)maskable(Non)maskable(Non)maskable0xFFFC 14Timer_A5 TA1CCR0 CCIFG0 (see Note 2) Maskable 0xFFFA 13T
33、imer_A5TA1CCR1 to TACCR4 CCIFGs,and TAIFG (see Notes 1 and 2)Maskable 0xFFF8 12Comparator_A+ CAIFG Maskable 0xFFF6 11Watchdog Timer+ WDTIFG Maskable 0xFFF4 10USCI_A0/B0 ReceiveUCA0RXIFG (see Note 1),UCB0RXIFG (SPI mode), orUCB0STAT UCALIFG, UCNACKIFG, UCSTTIFG,UCSTPIFG (I2C mode)(see Note 1)Maskable
34、 0xFFF2 9USCI_A0/B0 TransmitUCA0TXIFG (see Note 1),UCB0TXIFG (SPI mode), orUCB0RXIFG and UCB0TXIFG (I2C mode)(see Note 1)Maskable 0xFFF0 8ADC10 ADC10IFG (see Note 2) Maskable 0xFFEE 7Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0xFFEC 6Timer_A3TACCR1 CCIFG1 and TACCR2 CCIFG2,TAIFG (see Notes 1 and 2
35、)Maskable 0xFFEA 5I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0xFFE8 40xFFE6 30xFFE4 2I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0xFFE2 1Basic Timer1/RTC BTIFG Maskable 0xFFE0 0, lowestNOTES: 1. Multiple source flags2. Interrupt flags are
36、located in the module.3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).(Non)maskable:theindividualinterrupt-enablebitcandisableaninterruptevent,butthegeneral-interruptenablecannotdisableit.4. Access and key violations,
37、KEYV and ACCVIFG.MSP430F41x2MIXED SIGNAL MICROCONTROLLERSLAS648D - APRIL 2009 - REVISED SEPTEMBER 201013POST OFFICE BOX 655303DALLAS, TEXAS 75265special function registersMostinterruptandmodule-enablebitsarecollectedinthelowestaddressspace.Special-functionregisterbitsnotallocatedtoafunctionalpurpose
38、arenotphysicallypresentinthedevice.Thisarrangementprovidessimplesoftware access.interrupt enable 1 and 2Adres7654321000hACCVIE NMIIE OFIE WDTIErw-0 rw-0 rw-0 rw-0WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdogtimer is configured in interval timer mode
39、.OFIE Oscillator fault enableNMIIE (Non)maskable interrupt enableACCVIE Flash access violation interrupt enableAdres7654321001hBTIE UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIErw-0 rw-0 rw-0 rw-0 rw-0UCA0RXIE USCI_A0 receive interrupt enableUCA0TXIE USCI_A0 transmit interrupt enableUCB0RXIE USCI_B0 receive i
40、nterrupt enableUCB0TXIE USCI_B0 transmit interrupt enableBTIE Basic timer interrupt enableMSP430F41x2MIXED SIGNAL MICROCONTROLLERSLAS648D - APRIL 2009 - REVISED SEPTEMBER 201014 POST OFFICE BOX 655303DALLAS, TEXAS 75265interrupt flag register 1 and 2Adres7654321002hNMIIFG RSTIFG PORIFG OFIFG WDTIFGr
41、w-0 rw-(0) rw-(1) rw-1 rw-(0)WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.Reset on VCCpower-up or a reset condition at RST/NMI pin in reset mode.OFIFG Flag set on oscillator faultRSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in re
42、set mode. Reseton VCCpower-up.PORIFG Power-on interrupt flag. Set on VCCpower-up.NMIIFG Set via RST/NMI-pinAdres7654321003hBTIFGUCB0TXIFGUCB0RXIFGUCA0TXIFGUCA0RXIFGrw-0 rw-1 rw-0 rw-1 rw-0UCA0RXIFG USCI_A0 receive interrupt flagUCA0TXIFG USCI_A0 transmit interrupt flagUCB0RXIFG USCI_B0 receive inter
43、rupt flagUCB0TXIFG USCI_B0 transmit interrupt flagBTIFG Basic Timer1 interrupt flagLegend rw:rw-0,1:Bit can be read and written.Bit can be read and written. It is Reset or set by PUC.Bit can be read and written. It is Reset or set by POR.rw-(0,1):SFR bit is not present in deviceMSP430F41x2MIXED SIGN
44、AL MICROCONTROLLERSLAS648D - APRIL 2009 - REVISED SEPTEMBER 201015POST OFFICE BOX 655303DALLAS, TEXAS 75265memory organizationMSP430F4152 MSP430F4132MemoryMain: interrupt vectorMain: code memorySizeFlashFlash16KB0FFFFh - 0FFE0h0FFFFh - 0C000h8KB0FFFFh - 0FFE0h0FFFFh - 0E000hInformation memory SizeFl
45、ash256 Byte010FFh - 01000h256 Byte010FFh - 01000hBoot memory SizeROM1KB0FFFh - 0C00h1KB0FFFh - 0C00hRAM Size 512B03FFh - 0200h512B03FFh - 0200hPeripherals 16-bit8-bit8-bit SFR01FFh - 0100h0FFh - 010h0Fh - 00h01FFh - 0100h0FFh - 010h0Fh - 00hbootstrap loader (BSL)The MSP430 BSL enables users to progr
46、am the flash memory or RAM using a UART serial interface. Accessto the MSP430 memory via the BSL is protected by user-defined password. For complete description of thefeatures of the BSL and its implementation, see the MSP430 Memory Programming Users Guide, literaturenumber SLAU265.BSL FUNCTION PM P
47、ACKAGE PINS RGZ PACKAGE PINSData transmit 53 - P1.0 37 - P1.0Data receive 52 - P1.1 36 - P1.1flash memory (Flash)The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. TheCPUcanperformsingle-byteandsingle-wordwritestotheflashmemory.Featuresoftheflashmemo
48、ryinclude:D Flash memory has n segments of main memory and four segments of information memory (A to D) of64 bytes each. Each segment in main memory is 512 bytes in size.D Segments 0 to n may be erased in one step, or each segment may be individually erased.D Segments A to D can be erased individual
49、ly, or as a group with segments 0 to n.Segments A to D are also called information memory.MSP430F41x2MIXED SIGNAL MICROCONTROLLERSLAS648D - APRIL 2009 - REVISED SEPTEMBER 201016 POST OFFICE BOX 655303DALLAS, TEXAS 75265peripheralsPeripherals are connected to the CPU through data, address, and control buses and can be handled using allinstructions. For complete module descriptions, see the MSP430x4xx F
