1、 1. General description The 74LVC245A; 74LVCH245A are 8-bit transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features an output enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. OE controls th
2、e outputs so that the buses are effectively isolated. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The 74LVCH245A bus hold on data inputs eliminates
3、the need for external pull-up resistors to hold unused inputs. 2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Inputs accept voltages up to 5.5 V High-impedan
4、ce when V CC= 0 V Bus hold on all data inputs (74LVCH245A only) Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified
5、from 40 C to +85 C and 40 C to +125 C 74LVC245A; 74LVCH245A Octal bus transceiver; 3-state Rev. 8 28 June 2013 Product data sheet74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 8 28 June 2013 2 of 1
6、8 NXP Semiconductors 74LVC245A; 74LVCH245A Octal bus transceiver; 3-state 3. Ordering information4. Functional diagramTable 1. Ordering information Type number Package Temperature range Name Description Version 74LVC245AD 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm
7、 SOT163-1 74LVCH245AD 74LVC245ADB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 74LVCH245ADB 74LVC245APW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74LVCH245APW 74LVC245ABQ 40 C to +125 C D
8、HVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 4.5 0.85 mm SOT764-1 74LVCH245ABQ 74LVC245ABX 40 C to +125 C DHXQFN20 plastic dual in-line compatible thermal enhanced extremely thin quad flat package; no leads; 20 terminals; body
9、 4.5 2.5 0.5 mm SOT1045-2 74LVCH245ABX Fig 1. Logic diagram Fig 2. IEC logic symbol 2 1 DIR 18 19 B0 B1 B2 B3 B4 B5 B6 B7 3 17 4 16 5 15 6 14 7 13 8 12 9 A0 A1 A2 A3 A4 A5 A6 A7 11 OE mna174 17 3 1 19 2 1 16 4 15 5 14 6 13 7 12 8 11 9 18 G3 3EN1 3EN2 2 mna17574LVC_LVCH245A All information provided i
10、n this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 8 28 June 2013 3 of 18 NXP Semiconductors 74LVC245A; 74LVCH245A Octal bus transceiver; 3-state 5. Pinning information 5.1 Pinning5.2 Pin description(1) This is not a supply pin. The substrate
11、 is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 3. Pin configuration for SO20 and (T)SSOP20 Fig 4. Pin configuration for
12、DHVQFN20 and DHXQFN20 74LVC245A 74LVCH245A DIR V CC A0 OE A1 B0 A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 GND B7 001aak292 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 001aak293 74LVC245A 74LVCH245A Transparent top view B6 A6 A7 B5 A5 B4 A4 B3 A3 B2 A2 B1 A1 B0 A0 OE GND B7 DIR V CC 9 12 8 13 7 14 6
13、 15 5 16 4 17 3 18 2 19 10 11 1 20 terminal 1 index area GND (1) Table 2. Pin description Symbol Pin Description DIR 1 direction control A0 to A7 2, 3, 4, 5, 6, 7, 8, 9 data input/output GND 10 ground (0 V) B0 to B7 18, 17, 16, 15, 14, 13, 12, 11 data input/output OE 19 output enable input (active L
14、OW) V CC 20 supply voltage74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 8 28 June 2013 4 of 18 NXP Semiconductors 74LVC245A; 74LVCH245A Octal bus transceiver; 3-state 6. Functional description1 H
15、= HIGH voltage level; L = LOW voltage level; X = dont care; Z = high impedance OFF-state. 7. Limiting values1 The minimum input voltage ratings may be exceeded if the input current ratings are observed. 2 The output voltage ratings may be exceeded if the output current ratings are observed. 3 For SO
16、20 packages: above 70 C derate linearly with 8 mW/K. For (T)SSOP20 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN20 and DHXQFN20 packages: above 60 C derate linearly with 4.5 mW/K. Table 3. Function selection 1 Inputs Inputs/outputs OE DIR An Bn L L An = Bn inputs L H inputs Bn = An
17、HXZZ Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage 0.5 +6.5 V I IK input clamping current V I V CCor V O 0V - 50 mA V O output voltage output HIGH
18、 or LOW 2 0.5 V CC +0. 5 V output 3-state 2 0.5 +6.5 V I O output current V O =0V t oV CC - 50 mA I CC supply current - 100 mA I GND ground current 100 - mA T stg storage temperature 65 +150 C P tot total power dissipation T amb = 40 C to +125 C 3 -5 0 0m W74LVC_LVCH245A All information provided in
19、this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 8 28 June 2013 5 of 18 NXP Semiconductors 74LVC245A; 74LVCH245A Octal bus transceiver; 3-state 8. Recommended operating conditions9. Static characteristicsTable 5. Recommended operating conditi
20、ons Symbol Parameter Conditions Min Typ Max Unit V CC supply voltage 1.65 - 3.6 V functional 1.2 - 3.6 V V I input voltage 0 - 5.5 V V O output voltage output HIGH or LOW 0 - V CC V output 3-state 0 - 5.5 V T amb ambient temperature in free air 40 - +125 C t/ V input transition rise and fall rate V
21、CC= 1.2 V to 2.7 V 0 - 20 ns/V V CC= 2.7 V to 3.6 V 0 - 10 ns/V Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ 1 Max Min Max V IH HIGH-level input voltage V CC=
22、1.2 V 1.08 - - 1.08 - V V CC= 1.65 V to 1.95 V 0.65 V CC - - 0.65 V CC -V V CC= 2.3 V to 2.7 V 1.7 - - 1.7 - V V CC= 2.7 V to 3.6 V 2.0 - - 2.0 - V V IL LOW-level input voltage V CC= 1.2 V - - 0.12 - 0.12 V V CC= 1.65 V to 1.95 V - - 0.35 V CC - 0.35 V CC V V CC= 2.3 V to 2.7 V - - 0.7 - 0.7 V V CC=
23、 2.7 V to 3.6 V - - 0.8 - 0.8 V V OH HIGH-level output voltage V I =V IH or V IL I O = 100 A; V CC = 1.65 V to 3.6 V V CC 0.2 - - V CC 0.3 - V I O = 4m A ; V CC= 1.65 V 1.2 - - 1.05 - V I O = 8m A ; V CC= 2.3 V 1.8 - - 1.65 - V I O = 12 mA; V CC= 2.7 V 2.2 - - 2.05 - V I O = 18 mA; V CC= 3.0 V 2.4 -
24、 - 2.25 - V I O = 24 mA; V CC= 3.0 V 2.2 - - 2.0 - V V OL LOW-level output voltage V I =V IH or V IL I O =10 0 A; V CC = 1.65 V to 3.6 V -0 . 2-0 . 3V I O =4m A ; V CC= 1.65 V - - 0.45 - 0.65 V I O =8m A ; V CC= 2.3 V - - 0.6 - 0.8 V I O =1 2m A ; V CC= 2.7 V - - 0.4 - 0.6 V I O =2 4m A ; V CC= 3.0
25、V - - 0.55 - 0.8 V I I input leakage current V I = 5.5 V or GND; V CC =3 . 6V 2 - 0.1 5- 20 A74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 8 28 June 2013 6 of 18 NXP Semiconductors 74LVC245A; 74LV
26、CH245A Octal bus transceiver; 3-state 1 All typical values are measured at V CC= 3.3 V (unless stated otherwise) and T amb =2 5 C. 2 The bus hold circuit is switched off when V I V CCallowing 5.5 V on the input terminal. 3 For I/O ports the parameter I OZincludes the input leakage current. 4 Valid f
27、or data inputs of bus hold parts only (74LVCH245A). Note that control inputs do not have a bus hold circuit. 5 The specified sustaining current at the data input holds the input below the specified V Ilevel. 6 The specified overdrive current at the data input forces the data input to the opposite in
28、put state. I OZ OFF-state output current V I =V IH or V IL ; V O =5 .5Vo rG N D; V CC =3 . 6V 3 - 0.1 5- 20 A I OFF power-off leakage current V I or V O =5 . 5V ; V CC= 0.0 V - 0.1 10 - 20 A I CC supply current V I =V CC or GND; I O =0A; V CC =3 . 6V -0 . 11 0-4 0 A I CC additional supply current pe
29、r input pin; V I =V CC 0.6 V; I O =0A; V CC = 2.7 V to 3.6 V - 5 500 - 5000 A C I input capacitance V CC = 0 V to 3.6 V; V I =G N Dt oV CC -4 . 0-p F C I/O input/output capacitance V CC = 0 V to 3.6 V; V I =G N Dt oV CC -1 0-p F I BHL bus hold LOW current V CC= 1.65; V I= 0.58 V 45 10 - - 10 - A V C
30、C= 2.3; V I= 0.7 V 30 - - 25 - A V CC= 3.0; V I= 0.8 V 75 - - 60 - A I BHH bus hold HIGH current V CC= 1.65; V I= 1.07 V 45 10 - - 10 - A V CC= 2.3; V I= 1.7 V 30 - - 25 - A V CC= 3.0; V I= 2.0 V 75 - - 60 - A I BHLO bus hold LOW overdrive current V CC= 1.95 V 200 - - 200 - A V CC= 2.7 V 300 - - 300
31、 - A V CC= 3.6 V 46 500 - - 500 - A I BHHO bus hold HIGH overdrive current V CC= 1.95 V 200 - - 200 - A V CC= 2.7 V 300 - - 300 - A V CC= 3.6 V 46 500 - - 500 - A Table 6. Static characteristics continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Para
32、meter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ 1 Max Min Max74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 8 28 June 2013 7 of 18 NXP Semiconductors 74LVC245A; 74LVCH245A Octal bus tran
33、sceiver; 3-state 10. Dynamic characteristics1 t pdis the same as t PLHand t PHL . t enis the same as t PZLand t PZH . t disis the same as t PLZand t PHZ . 2 Typical values are measured at T amb =2 5 C and V CC= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. 3 Skew between any two outputs of the
34、same package switching in the same direction. This parameter is guaranteed by design. 4 C PD is used to determine the dynamic power dissipation (P D in W). P D =C PD V CC 2 f i N+ (C L V CC 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz C L = output load capacitance in pF
35、 V CC = supply voltage in Volts N = number of inputs switching (C L V CC 2 f o ) = sum of the outputs. Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ 2 Max Min Max t
36、pd propagation delay nAn to nBn; nBn to nAn; see Figure 5 1 V CC = 1.2 V - 17.0 - - - ns V CC= 1.65 V to 1.95 V 1.5 6.5 14.6 1.5 16.9 ns V CC= 2.3 V to 2.7 V 1.0 3.4 7.6 1.0 8.7 ns V CC= 2.7 V 1.5 3.4 7.3 1.5 9.5 ns V CC= 3.0 V to 3.6 V 1.5 2.9 6.3 1.5 8.0 ns t en enable time nOE to nAn, nBn; see Fi
37、gure 6 1 V CC = 1.2 V - 22.0 - - - ns V CC= 1.65 V to 1.95 V 1.9 8.3 19.5 1.9 22.5 ns V CC= 2.3 V to 2.7 V 1.5 4.6 10.7 1.5 12.4 ns V CC= 2.7 V 1.5 4.8 9.5 1.5 12.0 ns V CC= 3.0 V to 3.6 V 1.5 3.7 8.5 1.5 11.0 ns t dis disable time nOE to nAn, nBn; see Figure 6 1 V CC = 1.2 V - 12.0 - - - ns V CC= 1
38、.65 V to 1.95 V 2.9 5.5 12.3 2.9 14.2 ns V CC= 2.3 V to 2.7 V 1.0 3.1 7.1 1.0 8.2 ns V CC= 2.7 V 1.5 3.9 8.0 1.5 10.0 ns V CC= 3.0 V to 3.6 V 1.7 3.6 7.0 1.7 9.0 ns t sk(o) output skew time 3 - - 1.0 - 1.5 ns C PD power dissipation capacitance per input; V I =GN Dt oV CC 4 V CC= 1.65 V to 1.95 V - 7
39、.7 - - - pF V CC= 2.3 V to 2.7 V - 11.3 - - - pF V CC= 3.0 V to 3.6 V - 14.4 - - - pF74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 8 28 June 2013 8 of 18 NXP Semiconductors 74LVC245A; 74LVCH245A O
40、ctal bus transceiver; 3-state 11. AC waveformsSee Table 8 for measurement points V OLand V OHare typical output voltage levels that occur with the output load. Fig 5. Input (An, Bn) to output (Bn, An) propagation delays and output transition times mna176 An,Bn input Bn,An output t PLH t PHL GND V I
41、V M V M V M V M V OH V OL See Table 8 for measurement points V OLand V OHare typical output voltage levels that occur with the output load. Fig 6. Enable and disable times mna367 t PLZ t PHZ outputs disabled outputs enabled V Y V X outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-
42、to-HIGH OE input V I V OL V OH V CC V M GND GND t PZL t PZH V M V M Table 8. Measurement points Supply voltage V M Input V CC V I t r =t f V X V Y 1.2 V 0.5 V CC V CC 2.5 ns V OL+ 0.15 V V OH 0.15 V 1.65 V to 1.95 V 0.5 V CC V CC 2.5 ns V OL+ 0.15 V V OH 0.15 V 2.3 V to 2.7 V 0.5 V CC V CC 2.5 ns V
43、OL+ 0.15 V V OH 0.15 V 2. 7V 1. 5V 2 .7V 2.5 ns V OL+ 0.3 V V OH 0.3 V 3 . 0V t o 3 . 6V 1 . 5V 2 . 7V 2.5 ns V OL+ 0.3 V V OH 0.3 V74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 8 28 June 2013 9 o
44、f 18 NXP Semiconductors 74LVC245A; 74LVCH245A Octal bus transceiver; 3-stateTest data is given in Table 9. Definitions for test circuit: R L= Load resistance. C L= Load capacitance including jig and probe capacitance. R T= Termination resistance should be equal to output impedance Z oof the pulse ge
45、nerator. V EXT= External voltage for measuring switching times. Fig 7. Test circuit for measuring switching times V M V M t W t W 10 % 90 % 0 V V I V I negative pulse positive pulse 0 V V M V M 90 % 10 % t f t r t r t f 001aae331 V EXT V CC V I V O DUT C L R T R L R L G Table 9. Test data Supply vol
46、tage Input Load V EXT V I t r , t f C L R L t PLH , t PHL t PLZ , t PZL t PHZ , t PZH 1.2 V V CC 2 ns 30 pF 1 k open 2 V CC GND 1.65 V to 1.95 V V CC 2 ns 30 pF 1 k open 2 V CC GND 2.3 V to 2.7 V V CC 2 ns 30 pF 500 open 2 V CC GND 2. 7V 2 . 7V 2.5 ns 50 pF 500 open 2 V CC GND 3. 0Vto3. 6V 2 . 7V 2.
47、5 ns 50 pF 500 open 2 V CC GND74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 8 28 June 2013 10 of 18 NXP Semiconductors 74LVC245A; 74LVCH245A Octal bus transceiver; 3-state 12. Package outlineFig 8
48、. Package outline SOT163-1 (SO20) UNIT A max. A 1 A 2 A 3 b p cD (1) E (1) (1) eH E LL p Q Z y w v REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATEIEC JEDEC JEITA mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4SOT163-1 10 20 w M b p detail X Z e 11 1 D y 0.25075E04 MS-013 pin 1 index 0.1 0.012 0.
