1、IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011 485Nanosecond Delay Floating High Voltage LevelShifters in a 0.35 22m HV-CMOS TechnologyYashodhan Moghe, Torsten Lehmann, Senior Member, IEEE, and Tim Piessens, Member, IEEEAbstractWe present novel circuits for high-voltage digital
2、levelshifting with zero static power consumption. The conventionaltopology is analysed, showing the strong dependence of speed anddynamic power on circuit area. Novel techniques are shown tocircumvent this and speed up the operation of the conventionallevel-shifter architecture by a factor of 510 ty
3、pically and 30190in the worst case. In addition, these circuits use 50% less siliconarea and exhibit a factor of 2080 lower dynamic power consump-tion typically. Design guidelines and equations are given to makethe design robust over process corners, ensuring good productionyield. The circuits were
4、fabricated in a 0.35 m high-voltageCMOS process and verified. Due to power and IO speed limitationon the test chip, a special ring oscillator and divider structure wasused to measure inherent circuit speed.Index TermsCMOS, DMOS, fast, floating, high speed, highvoltage, high-speed, high-voltage, HV,
5、HV CMOS, HV-CMOS,HVCMOS, level shifter, level-shifter, low power, low-power, re-duced area, ultra fast, ultra-fast.I. INTRODUCTIONMODERN CMOS triple-well processes offer HV ex-tensions via special DMOS or drain-extended MOS(hereafter simply referred to as DMOS) transistors and N-wellsthat can float
6、up to high voltages above the chip substrate. It iscommon practice to place low voltage (LV) circuitry in thesefloating wells and communicate between the various voltagedomains via DMOS cascodes, particularly for digital controlsignals. Various techniques have been described in the literature112. Wh
7、ile these designs are useful for their applications,they have disadvantages, as shown in Table II:1) Low switching speed 1, 2: This is due to the high gateand drain capacitances of DMOS transistors or the delaythrough a LV transistor stack2) Large silicon area 1, 2, : This is due to the inability to
8、share floating N-wells among PDMOS transistors or thelarge area of a LV transistor stackManuscript received April 23, 2010; revised August 08, 2010; accepted Oc-tober 12, 2010. Date of publication December 10, 2010; date of current versionJanuary 28, 2011. This paper was approved by Associate Editor
9、 Philip K. T.Mok. This work was supported by Cochlear Ltd.Y.MogheiswiththeSilannaGroup,SydneyOlympicPark,Australia(e-mail:).T. Lehmann is with the School of Electrical Engineering and Telecom-munications, University of New South Wales, Sydney, Australia (e-mail:tlehmannunsw.edu.au).T. Piessens is wi
10、th ICsense, B-3001 Leuven, Belgium (e-mail: ).Color versions of one or more of the figures in this paper are available onlineat http:/ieeexplore.ieee.org.Digital Object Identifier 10.1109/JSSC.2010.2091322TABLE ISIMULATED AND MEASURED RESULTS3) Staticpowerconsumption39:Notsuitableforbattery-powered
11、(especially implantable) applications4) Dynamic control signals 4, 10: This increases systemcomplexity, especially for arrays of level shifters5) High voltage capacitors 11, 12: In many processes, HVcapacitors can be constructed only with normal routingmetals(overlaporfingerarrangement),requiringlar
12、geareato obtain reasonable capacitance valuesThe novel techniques in this paper avoid the above draw-backs while simultaneously improving silicon area, speed anddynamic power consumption. The techniques described are ad-ditive, in that they build on each other, resulting in a perfor-manceincreaseeac
13、h time.Wefocuson implementationsthat re-quire only thin-oxide DMOS transistors (high drain-source anddrain-gatevoltagebutlowgate-sourcevoltage)astheseworkef-ficiently over a wide range of supply voltages; and furthermore,thick-oxide DMOS transistors are not always available. Never-theless, many of t
14、hese techniques are generic and easily portedto thick-oxide DMOS designs.These techniques are robust and specifically account for wideprocess variations (process corners), ensuring high productionyield. The circuits, along with special test circuitry, were fabri-cated on a 0.35 m HV CMOS process and
15、 tested.II. CONVENTIONAL HV LEVEL SHIFTINGWhile many variations on HV level shifting circuits existin the literature, we focus on those that draw no static supplycurrent and dont require HV capacitors. The classic designtransforms the well-known low voltage level shifter Fig. 1(a)to a HV equivalent
16、using DMOS cascodes 2 Fig. 1(b). In0018-9200/$26.00 2010 IEEE486 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011TABLE IICOMPARISON WITH PREVIOUS WORK BY OTHERSFig. 1. Basic level shifting: (a) low-voltage prototype; (b) transformed to HV; (c) with simple modifications. Device dim
17、ensions given in microns. Dashed boxesindicate separate N-wells. All devices are placed in N-wells. nMOS transistors are placed in P-wells inside N-wells (not directly in the P-substrate).Fig. 1(b), the NDMOS cascode transistors M1/M2 (with gatesconnected to ) protect the LV pull-down transistors. S
18、im-ilarly, the PDMOS transistors M3/M4 (with gates connected to) protect the floating LV circuitry sitting between theand rails. Dashed boxes indicate separate N-wells. Onmost HV CMOS processes,NDMOS transistors must each havetheir own N-well (the drain terminal).Even for this basic circuit, improve
19、ments can be made asshown in Fig. 1(c). The NDMOS transistors are used directly aspull-downs rather than as cascodes, saving some area. Two ad-ditional low-voltage nMOS transistors M7/M8 are also added tothe floating circuitry to prevent the sources of the PDMOS tran-sistors being pulled more than a
20、 diode drop below . Other-wise, even though a PDMOS transistor may be off, leakage canpull its source down by several volts, weakening or destroyingthe gate oxide. Khorasani et al. 9 used resistor pull-ups toachieve the same effect, but with the disadvantage of dissipatingstatic power.A. Device Sizi
21、ng for DC OperationIn this section, we derive design equations for DC operationfor the LV and HV circuits in Fig. 1 to show the difficulty in theLV-to-HV transformation. To explicitly avoid negative quanti-ties in the algebra, we use the symbols and to denoteN-channel and P-channel threshold voltage
22、s respectively. Fur-thermore, for brevity we use , with a subscript indi-cating N-channel or P-channel.For the LV prototype in Fig. 1(a), consider the case whereis high. In this state, the gates of M1 and M3 are both at .Toflip the state of the level shifter, M1 needs to be sized relativeto M3 such
23、that when the gate of M1 is set to and thegate of M3 is still at , the common drain voltage can bepulleddownto atleast below otherwisethelatchedstate cannot be flipped quickly. By symmetry, M2 and M4 aresized the same way. Under these conditions, M1 is in the activeregion (assumingsimilar threshold
24、voltagesfor P and N channeltransistors and ), while M3 is in the triode region.We assume M3 is in the linear triode region to conservativelyoverestimate its strength.The currents through M1 and M3 are given by:MOGHE et al.: NANOSECOND DELAY FLOATING HIGH VOLTAGE LEVEL SHIFTERS IN A 0.35 m HV-CMOS TE
25、CHNOLOGY 487Since M1 and M3 pass the same current, we equate the twoequations to derive the following design equation:(1)For good yield, the NMOS/PMOS ratio is set for the slowN/fast P corner with maximum and minimum .FortheHVtransformedcaseinFig.1(c),thesituationisquitedifferent. As M1 turns on, is
26、 pulled down, and since M3 ison, follows. However, as drops, the gate drive on M3 de-creases, making the pulldown weaker. Therefore, it can be seenthattheratioofM3toM5isthecriticaldesignparameter.Again,M2, M4 and M6 are sized to make the circuit symmetrical. Inthe following equations, we set for alg
27、e-braic brevity and solve for the case where .As for the LV case, M5 is conservatively taken to be in thelinear triode region and the current through it is given byIf , which is easily achieved with a minimum sizeM1, then M3 is in the active region with current:where the additional subscript is used
28、 to indicate DMOS.Equating and gives the following design equation:(2)Firstly, from the denominator of (2), the floating voltage do-main must be greater than . Oth-erwise, M3 works in the subthreshold region during pulldown,which makes for a very large ratio in (2). In simulation withequal to 1.4 V
29、(approximately two threshold volt-ages), device ratios in excess of 100 were required for correctDC operation of the level shifter, confirming the above calcula-tion. Secondly, for good production yield, the sizing should bedone for the slow P corner (strong/weak N is irrelevant here, butrelevant in
30、 later sections).The difficulty in going from the LV case to the HV case isapparent when the sizing ratios in (1) and (2) are evaluated. Fordesignpurposes, wasused(approximately three threshold voltages), and all device dimen-sions given in this paper are for these conditions. For many 0.35m CMOS pr
31、ocesses (including this one), the ratio isnominally equal to 1/3, mainly due to the ratio of hole to elec-tron mobility, but in the fast P/slow N corner this increases to1/2. In the fast P/slow N corner, the values for andare approximately equal to 0.5 V and 0.7 V respectively for thisprocess.Undert
32、heseconditions,(1)dictatesadevicesizingratio.For the HV case, the critical device sizing ratio is muchhigher. In general, and track each other, and in theslow P corner are both approximately equal to 0.8 V for thisprocess. The ratio for most HV processes typicallyranges from 2 to 5 and this is set b
33、y the tradeoff betweenon-resistance and breakdown voltage for DMOS transistors.The DMOS transistors we used had a breakdown voltage of14 V, with a ratio of 2. Under these conditions, (2)dictates a device sizing ratio forM3/M5. This corresponds to the dimensions in this paper. Insimulation in the slo
34、w P corner, we found that DC operationof the circuit was compromised below ,which confirms the above calculation.M1 is also scaled relative to M5 according to the followingequation (which is very similar to (1):(3)Again,thescalingisdonefortheslowN/fastPcorner.Forthetechnology we used, the ratio for
35、M1/M5was equal to 0.75. Note that this is higher than the case forthe LV level shifter due to the lower ratio of for theNDMOS case. As shown in the next section, a minimum sizedM1 is more than sufficient.B. Dynamic Performance CalculationsThe delay through the basic HV level shifter is composed ofth
36、e transient behaviour on the four circuit nodes , ,and shown in Fig. 1(c). Fig. 2 shows a top view and wafercross section of the devices M1, M3, and M5. The various gateandjunction capacitancesareshown, toaidin understandingthetransient behaviour of the circuit. The diagram is not to scale.Consider
37、the case when is initially low. To switch thelevel shifter, the following sequence takes place:1) goes high, charging up the gate capacitanceof M1. The inverter I1 similarly discharges the gate capac-itance of M22) The node begins to drop rapidly as shown in Fig. 4.Nodes and have the largest parasit
38、ic capacitance,as explained below, however M1 is switched on verystrongly in the active region and discharges the capaci-tanceon quickly.Thenode isinahigh-impedancestatebutremainssteadyduetothecapacitanceonthenode.3) Node quickly follows down until it reaches avoltage at least below , as determined
39、by therelative sizing of M3 and M5. We denote the time delaythus far . At this time, the node experiences alarge step increase.4) Node charges up to the same voltage as and wedenote this time delay5) Node charges up slowly and linearly as shown inFig. 4 due to the combination of large parasitic capa
40、citanceand low current through the weakly switched on devicesM4 and M6 that are both in the active region. We denotethis time delay6) Once chargesuptothesamevoltageas ,theybothcharge up towards the rail. As this happens, nodedrops further down and the positive transition oncompletes. We denote this
41、time delay .The total delay through the level shifter is composed of thesum . is quite small because although theparasitic capacitance on node is large, the pulldown strength488 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011Fig. 2. Top view and cross section of important devices
42、 in basic HV level-shifter with critical dimensions marked. Diagram not to scale.Fig. 3. Equivalent circuit during time84 . Dashed line indicates virtual connec-tion.of M1 and M3 is high, resulting in a fast transient. is alsosmall because the required voltage swing on node is smalland can be accomp
43、lished quickly. is large due to the combi-nation of high parasitic capacitance on node and the lowpullup capability of M6. can also be large because M3 isonly able to pull quickly to within a threshold voltage of. Thereafter, only subthreshold current can discharge thenode further. , , , are shown i
44、n Fig. 4.We now give a derivation of the parameter to show how itchangeswithdevicewidthandthevaluesof and .Wedo not give a derivation of since we show later in Section IIIhow to minimise it by various techniques.is the time that it takes node to charge from toabove that is, nearly through the entire
45、 voltage.During this time, nodes and are equal by reason of cir-cuit symmetry. M6 thus acts like a diode-connected transistor inthe active region. M4 is also in the active region. The currentsthrough M4 and M6 are given by(4)(5)For algebraic simplicity, we make the substitutionand . That is, weconsi
46、der to be the local ground potential and specifyvoltages relative to that. Equating currents through M4 and M6gives(6)However, from (2), we knowwhere and represent the threshold volt-ages for pMOS and PDMOS respectively in the slow P processcorner. Also, as explained earlier, and(PMOS and PDMOS tran
47、sistors track each otheracross process corners) and . Substi-tuting these into (6) and solving for , we get(7)Substituting this back into (4) gives(8)MOGHE et al.: NANOSECOND DELAY FLOATING HIGH VOLTAGE LEVEL SHIFTERS IN A 0.35 m HV-CMOS TECHNOLOGY 489Fig. 4. Transient operation of basic HV level sh
48、ifter. Delays 84 -84 (Section II-B) indicated.To understand the speed at which node charges up, weexamine the dynamic circuit consisting of ideal transistors andmajor parasitic capacitances shown in Fig. 3. The dashed lineshows the virtual diode connection of M6. In reality, the in-stantaneous curre
49、nts through M4 and M6 are not the same dueto the presence of . The current required to dischargeduring the transient actually flows through M4, thusincreasingthe voltageandmakingthevirtualdiodeconnec-tion of M6 not strictly valid. However, we verified in simulationthat the error in current associated with making the diode con-nection assumption is less than 10%, and is thus acceptable inorder to simplify the analysis.Node is a low-impedance node due to the virtual diodeconnection assumption, and hence
