1、1 PrerequisitesPreliminaryApplication ReportSPRAAA8A August 2006Implementing Serial Rapid I/O PCB Layout on aTMS320C6455 Hardware DesignTodd Hiers . DSP Hardware ApplicationsThis application report contains implementation instructions for the Serial Rapid I/O(SRIO) interface on the TMS320C6455 DSP d
2、evice. The approach to specifyinginterface timing and physical requirements for the SRIO interface is quite different thanprevious approaches for other interfaces.Serial Rapid I/O is an industry-standard high-speed switched-packet interconnect.Physical layer data transmission utilizes analog seriali
3、zer/deserializers (serdes) to feedlow-output-swing differential CML buffers. Proper printed circuit board (PCB) design forthis interface resembles analog or RF design, and is very different than traditionalparallel digital bus design.Due to this analog nature of SRIO, it is not possible to specify t
4、he interface in atraditional DSP digital interface manner. Furthermore, it is undesirable to specify theinterface in terms of the raw physical requirements laid out by the SRIO specification.Understanding the SRIO specification and producing a compliant PCB based on theexplicit and implicit requirem
5、ents there demands significant time, experience, andexpensive tools.For the TMS320C6455 SRIO interface, the approach is to reduce the specification to aset of easy-to-follow PCB routing rules. TI has performed the simulation and systemdesign work to ensure SRIO interface requirements are met. This d
6、ocument describesthe content of this SRIO implementation.Contents1 Prerequisites 12 TMS320C6455 Supported Serial RapidIO Devices 23 Description of the Serial Rapid I/O Hardware Design Files . 24 PCB Routing Rules . 25 Device Settings . 76 References . 10The goal of the C6455 collateral is to make sy
7、stem implementation easier for the customer by providingthe system solution. For this Serial RapidIO (SRIO) interface, it is not assumed that the system designer isfamiliar with SRIO, serializer-deserializer (SERDES) technology, or RF/Microwave PCB design. However,it is still expected that the PCB d
8、esign work be supervised by a knowledgeable high speed digital PCBdesigner and an assumption is made that the PCB designer is using established high speed design rules.SPRAAA8A August 2006 Implementing Serial Rapid I/O PCB Layout on a TMS320C6455 Hardware Design 1Submit Documentation F2 TMS320C6455
9、Supported Serial RapidIO Devices3 Description of the Serial Rapid I/O Hardware Design Files4 PCB Routing Rules4.1 Minimum PCB Stackup4.2 General Trace/Space and Via SizesPreliminaryTMS320C6455 Supported Serial RapidIO DevicesRapidIO is an industry-standard high-speed switched-packet interconnect. Th
10、e RapidIO specificationallows a device to connect to any other device, so long as the two devices conform to a commonphysical-layer specification. TI DSPs support connecting to any Serial RapidIO device that complies withthe Serial RapidIO specification revision 1.2 or later.The SRIO Hardware Design
11、 files included with this report are described in Table 1 .Table 1. SRIO Hardware Design FilesFile Name DescriptionDSP_SRIO_Example.brd Allegro 15.x design database file containing the PCB layout. This file can be viewedand edited using Cadence Allegro PCB design tools. It can also be viewed using t
12、hefree Allegro viewer compatible with version 15.x databases. The free viewer can bedownloaded from http:/ .DSP_SRIO_Example.dsn Reference design SRIO schematics in ORCAD design, project, and .pdf file formats.DSP_SRIO_Example.opj These schematics contain circuitry for the SRIO interface.DSP_SRIO_Ex
13、ample.pdfThe minimum PCB stackup for routing the TMS320C6455 is a six-layer stackup as described in Table 2 .Table 2. Minimum PCB StackupLayer Type Description1 Signal Top Routing2 Plane Ground3 Plane Split Power4 Signal Internal Routing5 Plane Ground6 Signal Bottom RoutingAdditional layers may be a
14、dded as needed. All layers with SRIO traces must be able to achieve 100 ohmsdifferential impedance.Note: The provided sample board file shows a twelve-layer stackup, but not all of these layersare necessary to use the SRIO interface.The key concern for RapidIO signal traces is to achieve 100 Ohm dif
15、ferential impedance. This differentialimpedance is impacted by trace width, trace spacing, distance between planes, and dielectric material.Verify with a proper PCB manufacturing tool that the trace geometry for all SRIO traces results in exactly100 Ohms differential impedance traces.Of secondary co
16、ncern is the insertion loss caused by the traces. Due to the skin effect, wider traces willhave lower losses than narrower ones. Therefore, longer SRIO runs should use wider traces for lowerloss. Layers in the stackup that are set to 100 Ohm differential impedance with wider traces may be lessdesira
17、ble for routing other signals. Table 3 shows recommendations for minimum trace width by SRIOsignal run lengthImplementing Serial Rapid I/O PCB Layout on a TMS320C6455 Hardware Design2 SPRAAA8A August 2006Submit Documentation F4.3 Serial RapidIO Interface Routing Requirements4.3.1 Receiver EndPrelimi
18、naryPCB Routing RulesTable 3. Minimum Trace WidthSignal Run Length, up to Minimum trace width10 in / 25 cm 4 mil / .1 mm20 in / 50 cm 6 mil / .15 mm30 in / 75 cm 8 mil / .2 mmThe C6455 sample PCB is routed using 4 mil traces and 4 mil minimum trace spacing. 100 Ohmsdifferential impedance is achieved
19、 with 4 mil traces and 10 mil spaces on the Top and Bottom layers, and4 mil traces with 5 mil spaces on internal layers. Escape and general SRIO routing vias have 8 mil holeswith 18 mil pads. Micro and/or blind/buried vias are neither required nor prohibited.The PCB BGA pad requirements for the C645
20、5 device are documented by the Flip Chip Ball Grid ArrayPackage Reference Guide ( SPRU811a ), available at . The C6455 is a 0.8 mm ball pitch partand should follow the 0.8 mm guidelines. The PCB BGA pad requirements for the SRIO link partnerdevice should follow its manufacturers guidelines.The appr
21、oach used in this reference design for specifying suitable RapidIO routing breaks the physicalconnection down into three component pieces: receiver end, transmitter end, and interconnect. Thereceiver and transmitter end are the pieces closest to the packages of the connected devices. Thereceiver end
22、 goes from the BGA pads to the capacitors. The transmitter end is simply the BGA escapepaths for the differential pairs. Those two pieces of the reference layout are designed to be copied exactlyinto the target board. The interconnect joins the receiver and transmitter ends, and it is not intended t
23、o becopied directly, as board placements will vary from the sample.Figure 1 below shows the connection on the receiver end. The trace from the BGA pad to the capacitorpad must be on the top layer. On the other side of the capacitor, it is recommended to via to another layer.The BGA breakout should b
24、e implemented exactly as shown. The trace widths and separation should bealtered based on the board stackup to meet the 100 differential impedance requirement. Also, tracesmay be necked down to escape the BGA, if necessary.An 0402 or smaller size, 0.1 f capacitor is recommended for AC coupling of th
25、e data lines.SPRAAA8A August 2006 Implementing Serial Rapid I/O PCB Layout on a TMS320C6455 Hardware Design 3Submit Documentation F4.3.2 Transmitter EndPreliminaryPCB Routing RulesFigure 1. Receiver END BGA BreakoutFigure 2 below shows the connection on the transmitter end. This trace may be on any
26、signal layerbesides the top. Internal layers are recommended for their superior shielding characteristics. The BGAbreakout should be implemented exactly as shown. The trace widths and separation should be alteredbased on the board stackup to meet the 100 differential impedance requirement. Also, tra
27、ces may benecked down to escape the BGA, if necessary.4 Implementing Serial Rapid I/O PCB Layout on a TMS320C6455 Hardware Design SPRAAA8A August 2006Submit Documentation F4.3.3 Interconnect4.3.4 Length MatchingPreliminaryPCB Routing RulesFigure 2. Transmitter End BGA BreakoutThe geometry of the tra
28、ces to link the transmitter and receiver ends is determined by the placement in thetarget system. Therefore, it is not possible to specify an exact layout for the interconnect. Instead, thetrace may be placed as required, so long as it meets the following requirements: Edge-coupled, matched-length (
29、 50 mils) differential pair No stubs No more than 30 inches (75cm) pin-to-pin, for 8-mil (.2mm) wide traces over FR4 material 100 differential impedance No more than 3 sets of vias (not including via for BGA breakout on transmit end) Other signals are separated by at least 2x the differential spacin
30、g Internal layers are strongly preferred. Avoid top and bottom layers If connectors are used, they must be of a suitable 100 ohm differential-impedance, high-speed type,and count as 1 ” of trace for each connector pair If cabling is used, it must be of a suitable controlled-impedance type (100 ohm d
31、ifferential or 50 ohmsingle ended), and counts as 1“ of trace for each 1 of cable. If a mid bus probe is used, it must follow both TI s and the probe manufacturer s guidelines, and countsas 2 ” of traceIf the SRIO peripheral will be used in 1x mode, then there is no lane-to-lane length matching requ
32、irement.If the SRIO peripheral will be used in 4x mode, then: All TX lanes connected to a device must all be +/- 5 inches (12.5 cm) in length from each other All RX lanes connected to a device must all be +/- 5 inches (12.5 cm) in length from each other There is no requirement that the TX lengths ma
33、tch the RX lengthsSPRAAA8A August 2006 Implementing Serial Rapid I/O PCB Layout on a TMS320C6455 Hardware Design 5Submit Documentation F4.3.5 Mid Bus Probe (Optional)4.3.6 Connectors (Optional)4.3.7 Cabling (Optional)PreliminaryPCB Routing RulesA mid bus probe can be used to observe traffic flowing
34、down a link. Because the probe requires a specialattachment point, it can degrade signal quality. The following rules must be observed to include a mid busprobe: Follow the Probe manufacturer s guidelines for probe pads and layout If the stubs can be kept under 250 mils (6.35 mm) then connecting the
35、 probe lands as stubs to thetransmission line is acceptable If the stubs cannot be kept under 250 mils (6.35 mm) then the probe lands should be connected in-linewith the rest of the transmission lineAny connectors used must be controlled impedance (50 Ohm single ended or 100 Ohm differential) andsui
36、table for microwave transmissions. Suitable connectors are typically categorized as “ backplane ” typeconnectors. The connectors should have less than 1 dB insertion loss below 6 GHz. Some suggestedconnectors are: CN074 AMC Connector Tyco Z-DOK Tyco Z-PAK HM ZdAny cabling used must be controlled imp
37、edance (50 Ohm single ended or 100 Ohm differential) andsuitable for microwave transmissions. Recommended cable types are listed below: 50 Ohm Coaxial Commonly used with SMA connectors, 4 cables required for 1x link, 16 for 4x linkq RG142q RG316q RG178 Infiniband assembled cables available in 1x and
38、 4x widthsImplementing Serial Rapid I/O PCB Layout on a TMS320C6455 Hardware Design6 SPRAAA8A August 2006Submit Documentation F4.4 Power Supply Requirements5 Device SettingsPreliminaryDevice SettingsThe power supply and bypassing requirements for SRIO are documented as part of the TMS320C6455Design
39、Guide and Comparisons to TMS320TC6416T ( SPRAA89 ).Figure 3. Power Plane SplitsSome of the SERDES register values should be set based on parameters from the physical PCB. Othersare not dependent on the PCB, but are set based on the SRIO electrical specification. The followingsections describe the re
40、commended settings for the receivers and transmitters. More information aboutthese registers can be found in the TMS320C645x Serial Rapid IO (SRIO) User s Guide ( SPRU976 ).SPRAAA8A August 2006 Implementing Serial Rapid I/O PCB Layout on a TMS320C6455 Hardware Design 7Submit Documentation F5.1 Recei
41、ve Channel ConfigurationPreliminaryDevice SettingsTable 4 lists the recommended settings for receiver channels that can be set in the SERDES ReceiveChannel Configuration Registers (SERDES_CFGRXn_CNTL).Table 4. SERDES Receive Channel Configuration Register SettingsBits Field Setting Description19:22
42、EQ 0001 Fully Adaptive Equalization18:16 CDR 000 First Order. Sufficient for SRIOclocking scheme(asynchronous with lowfrequency offset)15:14 LOS 00 Disabled. Loss of Signaldetection not used in SRIO13:12 ALIGN 01 Comma Alignment. SRIO usescomma alignment during laneinitialization10:8 TERM 001 Common
43、 point is 80% ofVDDT. This is the appropriatesetting for AC coupled lines7 INVPAIR 0 Non-inverted use when TXPconnects to RXP and TXNconnects to RXN1 Inverted use when TXPconnects to RXN and TXNconnects to RXP (1)6:5 RATE 00 Full Use for 3.125 GHz and2.5 GHz line rates01 Half Use for 1.25 GHz linera
44、te4:2 BUS-WIDTH 000 10-bit. SRIO uses 10-bitcharacter groups.0 ENRX 0 Disabled for unused lanes1 Enabled for active lanes(1) On inverted pairs, polarity inversion can be done at the receiver end or the transmitter end, but not bothImplementing Serial Rapid I/O PCB Layout on a TMS320C6455 Hardware De
45、sign8 SPRAAA8A August 2006Submit Documentation F5.2 Transmit Channel ConfigurationPreliminaryDevice SettingsTable 5 lists the recommended settings for transmitter channels that can be set in the SERDES TransmitChannel Configuration Registers (SERDES_CFGTXn_CNTL).Table 5. SERDES Transmit Channel Conf
46、iguration Register SettingsBits Field Setting Description16 ENFTP 1 Fixed Phase. Required for 4xmode. Do not care in 1x mode.15:12 DE 1000 -4.16 dB. Use for lines up to 10inches (25cm)1001 -4.86 dB. Use for lines up to14inches (35cm)1010 -5.61 dB. Use for lines up to 18inches (45cm)1011 -6.44 dB. Us
47、e for lines up to 22inches (55cm)1100 -7.35 dB. Use for lines up to 26inches (65cm)1101 -8.38 dB. Use for lines up to 30inches (75cm)11:9 SWING 100 750mV. Use for lines up to 10inches (25cm)101 1000mV. Use for lines up to 20inches (50cm)111 1375mV. Use for lines up to 30inches (75cm)8 CM 1 Raised Co
48、mmon Mode. Helpfulin preventing signal distortionat SWING amplitudes over750mV7 INVPAIR 0 Non-inverted use when TXPconnects to RXP and TXNconnects to RXN1 Inverted use when TXPconnects to RXN and TXNconnects to RXP (1)6:5 RATE 00 Full Use for 3.125 GHz and2.5 GHz line rates01 Half Use for 1.25 GHz l
49、inerate4:2 BUS WIDTH 000 10-bit. SRIO uses 10-bitcharacter groups.0 ENTX 0 Disabled for unused lanes1 Enabled for active lanes(1) On inverted pairs, polarity inversion can be done at the receiver end or the transmitter end, but not bothSPRAAA8A August 2006 Implementing Serial Rapid I/O PCB Layout on a TMS320C6455 Hardware Design 9Submit Document
