1、 EM78P152/3S 8-Bit Microcontroller with OTP ROM Product Specification DOC. VERSION 1.7 ELAN MICROELECTRONICS CORP. January 2009 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks
2、of ELAN Microelectronics Corporation. Copyright 20032009 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or c
3、ompleteness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made respon
4、sible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or materia
5、l. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Us
6、e of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS. Contents Product Specification (V1.7) 01.12.2009 i
7、ii Contents 1 General Description 1 2 Features . 1 3 Pin Assignment . 2 4 Pin Description 3 4.1 EM78P153S . 3 4.2 EM78P152S . 4 5 Functional Description . 5 5.1 Operational Registers. 5 5.1.1 R0 (Indirect Addressing Register) .5 5.1.2 R1 (Timer Clock /Counter) 5 5.1.3 R2 (Program Counter and Stack)6
8、 5.1.4 R3 (Status Register)7 5.1.5 R4 (RAM Select Register).8 5.1.6 R5 R6 (Port 5 Port 6) 8 5.1.7 RF (Interrupt Status Register) .8 5.1.8 R10 R2F.8 5.2 Special Function Registers. 9 5.2.1 A (Accumulator).9 5.2.2 CONT (Control Register).9 5.2.3 IOC5 IOC6 (I/O Port Control Register) 10 5.2.4 IOCB (Pul
9、l-down Control Register) .10 5.2.5 IOCC (Open-drain Control Register).10 5.2.6 IOCD (Pull-high Control Register).11 5.2.7 IOCE (WDT Control Register).11 5.2.8 IOCF (Interrupt Mask Register).12 5.3 TCC/WDT and Prescaler 12 5.4 I/O Ports .13 5.5 Reset and Wake-up 16 5.5.1 Reset .16 5.5.2 Summary of Re
10、gisters Initialized Values.18 5.5.3 Status of RST, T, and P of the Status Register20 5.6 Interrupt 21 5.7 Oscillator 22 5.7.1 Oscillator Modes22 5.7.2 Crystal Oscillator/Ceramic Resonators (Crystal).22 5.7.3 External RC Oscillator Mode.24 5.7.4 Internal RC Oscillator Mode 25 Contents iv Product Spec
11、ification (V1.7) 01.12.2009 5.8 Code Option Register. 26 5.8.1 Code Option Register (Word 0) 26 5.9 Power-on Considerations . 28 5.10 Programmable Oscillator Set-up Time . 28 5.11 External Power-on Reset Circuits. 28 5.12 Residue-Voltage Protection 29 5.13 Instruction Set 30 6 Absolute Maximum Ratin
12、gs . 33 7 Electrical Characteristics . 33 7.1 DC Characteristic . 33 7.2 AC Characteristic . 34 8 Timing Diagrams . 35 APPENDIX A Package Type. 36 B Package Information. 37 C Device Characteristics 40 Specification Revision History Doc. Version Revision Description Date 1.1 Initial version 1.2 Chang
13、ed the Initialized Register Values, Internal RC Drift Rate, DC and AC Electrical Characteristic 2003/05/02 1.3 Changed the Power-on reset contents 2003/06/25 1.4 Added the Device Characteristic at Section 6.3 2003/12/31 1.5 Added the IRC drift rate in the Features section 2006/01/16 1.6 Added EM78P1
14、52S SSOP 10-pin Package 2007/03/30 1.7 1. Modified the EM78P152S 10-pin SSOP Package name 2. Added Ceramic Resonators in the Oscillator section 3. Modified the contents of the Program Counter section 4. Modified the contents of IOCC in the Special Function Register 2009/01/12 EM78P152/3S 8-Bit Micro
15、controller with OTP ROM Product Specification (V1.7) 01.12.2009 1 (This specification is subject to change without further notice) 1 General Description The EM78P152/3S is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS technology. It has an on-chip 102413-bit Elect
16、rical One Time Programmable Read Only Memory (OTP-ROM). It provides a protection bit to prevent intrusion of users OTP memory code. Fifteen Code option bits are also available to meet users requirements. With its enhanced OTP-ROM feature, the EM78P152/3S provides a convenient way of developing and v
17、erifying users programs. Moreover, this OTP device offers the advantages of easy and effective program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his development code. 2 Features CPU configuration 1K13 bits on chip ROM 328 bits on-chip regis
18、ters (SRAM, general purpose) 5 level stacks for subroutine nesting Less than 1.5 mA at 5V/4MHz Typically 15 A, at 3V/32kHz Typically 1 A, during Sleep mode I/O port configuration 2 bidirectional I/O ports : P5, P6 12 I/O pins Wake-up port : P6 6 Programmable pull-down I/O pins 7 programmable pull-hi
19、gh I/O pins 7 programmable open-drain I/O pins External interrupt : P60 Operating voltage range: OTP version: Operating voltage range: 2.3V5.5V Operating temperature range: 070C Operating frequency range (base on 2 clocks): Crystal mode: DC20MHz/2clks 5V; DC100ns inst. cycle 5V DC8MHz/2clks 3V; DC25
20、0ns inst. cycle 3V DC4MHz/2clks 2.3V; DC500ns inst. cycle 2.3V ERC mode: DC4MHz/2clks 5V; DC500ns inst. cycle 5V DC4MHz/2clks 3V; DC500ns inst. cycle 3V DC4MHz/2clks 2.3V; DC500ns inst. cycle 2.3V IRC mode: Oscillation mode : 4MHz, 8MHz, 1MHz, 455kHz Process deviation : Typ 5.5%, Max 6% Temperature
21、deviation : 10% (0C70C ) The transient point of system frequency between HXT and LXT is 400kHz. Peripheral configuration 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt Three available interrupts: TCC overflow interrupt Input-port status chang
22、ed interrupt (wake-up from sleep mode) External interrupt Special features Programmable free running watchdog timer Power saving Sleep mode Selectable Oscillation mode Other features Programmable prescaler of oscillator set-up time One security register to prevent intrusion of users OTP memory code
23、One configuration register to match users requirement Two clocks per instruction cycle Package type: 14-pin DIP 300mil : EM78P153SP/S/J 14-pin SOP 150mil : EM78P153SN/S/J 10-pin SSOP 150mil : EM78P152SN/S/J Note: Green products do not contain hazardous substances. FAE: 135 9015 2895EM78P152/3S 8-Bit
24、 Microcontroller with OTP ROM 2 Product Specification (V1.7) 01.12.2009 (This specification is subject to change without further notice) 3 Pin Assignment (1) 14-Pin DIP/SOP 123458910EM78P153S6711121314P50P67P66VddP65/OSCIP64/OSCOP63/RSTP51P52P53VssP60/INTP61P62/TCCFigure 3-1 EM78P153SP/N/S/J (2) 10-
25、Pin SSOP 123458910EM78P152S67P67P66VddP65/OSCIP64/OSCOP63/RSTVssP60/INT P61P62/TCCFigure 3-2 EM78P152SN/S/J EM78P152/3S 8-Bit Microcontroller with OTP ROM Product Specification (V1.7) 01.12.2009 3 (This specification is subject to change without further notice) 4 Pin Description 4.1 EM78P153S Symbol
26、 Pin No. Type Function P66, P67 2, 3 I/O General purpose input/output pin Pull-high open-drain Wake up from sleep mode when the status of the pin changes. P65/OSCI 5 I/O General purpose input/output pin External clock signal input Input pin of XT oscillator Pull-high open-drain Wake up from sleep mo
27、de when the status of the pin changes. P64/OSCO 6 I/O General purpose input/output pin External clock signal input Input pin of XT oscillator Pull-high open-drain Wake up from sleep mode when the status of the pin changes. P63/RESET 7 I P63 is input pin only Internal Pull-high is on if defined as /R
28、ESET. If set as /RESET and remains at logic low, the device will be reset. Wake-up from sleep mode when pin status changes. Voltage on /RESET must not exceed Vdd during normal mode. P62/TCC 8 I/O General purpose input/output pin External Timer/Counter input Pull-high/Pull-down open-drain Wake up fro
29、m sleep mode when the status of the pin changes. P61 9 I/O General purpose input/output pin Pull-high/Pull-down open-drain Wake up from sleep mode when the status of the pin changes. Schmitt Trigger input during programming mode. P60/INT 10 I/O General purpose input/output pin Pull-high/Pull-down op
30、en-drain Wake up from sleep mode when the status of the pin changes. Schmitt Trigger input during programming mode. External interrupt pin triggered by a falling edge. P50, P51P52 1, 1314 I/O General purpose input/output pin Pull-down P53 12 I/O General purpose input/output pin VDD 4 Power supply VS
31、S 11 Ground FAE: 135 9015 2895EM78P152/3S 8-Bit Microcontroller with OTP ROM 4 Product Specification (V1.7) 01.12.2009 (This specification is subject to change without further notice) 4.2 EM78P152S Symbol Pin No. Type Function P66, P67 4, 3 I/O General purpose input/output pin Pull-high open-drain W
32、ake up from sleep mode when the status of the pin changes. P65/OSCI 6 I/O General purpose input/output pin External clock signal input Input pin of XT oscillator Pull-high open-drain Wake up from sleep mode when the status of the pin changes. P64/OSCO 7 I/O General purpose input/output pin External
33、clock signal input Input pin of XT oscillator Pull-high open-drain Wake up from sleep mode when the status of the pin changes. P63/RESET 8 I P63 is input pin only Internal Pull-high is on if defined as /RESET. If set as /RESET and remains at logic low, the device will be reset. Wake-up from sleep mo
34、de when pin status changes Voltage on /RESET must not exceed Vdd during normal mode. P62/TCC 9 I/O General purpose input/output pin External Timer/Counter input Pull-high/Pull-down open-drain Wake up from sleep mode when the status of the pin changes. P61 10 I/O General purpose input/output pin Pull
35、-high/Pull-down open-drain Wake up from sleep mode when the status of the pin changes. Schmitt Trigger input during programming mode. P60/INT 1 I/O General purpose input/output pin Pull-high/Pull-down open-drain Wake up from sleep mode when the status of the pin changes. Schmitt Trigger input during
36、 programming mode. External interrupt pin triggered by a falling edge. VDD 5 Power supply VSS 2 Ground EM78P152/3S 8-Bit Microcontroller with OTP ROM Product Specification (V1.7) 01.12.2009 5 (This specification is subject to change without further notice) 5 Functional Description InterruptControlle
37、rROMInstructionRegisterInstructionDecoderR2ALUStackACCR3R4Oscillator/TimingControlWDT TimerPrescalerR1 (TCC)RAMDATA and reset to “0” by WDT time-out. Bit 3 (P): Power down bit Set to “1” during power on or by a “WDTC“ command; and reset to “0” by a “SLEP“ command. Bit 2 (Z): Zero flag Set to “1“ if
38、the result of an arithmetic or logic operation is zero. Bit 1 (DC): Auxiliary carry flag Bit 0 (C): Carry flag FAE: 135 9015 2895EM78P152/3S 8-Bit Microcontroller with OTP ROM 8 Product Specification (V1.7) 01.12.2009 (This specification is subject to change without further notice) 5.1.5 R4 (RAM Sel
39、ect Register) Bits 7 6 are general-purpose read/write bits. See the Data Memory Configuration in Figure 5-3. 5.1.6 R5 R6 (Port 5 Port 6) R5 and R6 are I/O registers. Only the lower 4 bits of R5 are available. The upper 4 bits of R5 are fixed to 0. P63 is input only. 5.1.7 RF (Interrupt Status Regist
40、er) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - EXIF ICIF TCIF Note: “ 1 ” means with interrupt request “ 0 ” means no interrupt occurs Bits 7 3: Not used. Bit 2 (EXIF): External Interrupt Flag. Set by a falling edge on /INT pin, reset by software. Bit 1 (ICIF): Port 6 input status cha
41、nged interrupt flag. Set when Port 6 input changes, reset by software. Bit 0 (TCIF): TCC Overflow Interrupt Flag. Set when TCC overflows, reset by software. RF can be cleared by instruction but cannot be set. IOCF is the interrupt mask register. NOTE The result of reading RF is the “logic AND“ of RF
42、 and IOCF. 5.1.8 R10 R2F These are all 8-bit general-purpose registers. FAE: 135 9015 2895EM78P152/3S 8-Bit Microcontroller with OTP ROM Product Specification (V1.7) 01.12.2009 9 (This specification is subject to change without further notice) 5.2 Special Function Registers 5.2.1 A (Accumulator) Int
43、ernal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register. 5.2.2 CONT (Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - /INT TS TE PAB PSR2 PSR1 PSR0 Bit 7: Not used Bit 6
44、(/INT): Interrupt enable flag 0 : masked by DISI or hardware interrupt 1 : enabled by ENI/RETI instructions Bit 5 (TS): TCC signal source 0 : internal instruction cycle clock, P62 is a bidirectional I/O pin 1 : transition on TCC pin Bit 4 (TE): TCC Signal Edge 0 : increment if the transition from lo
45、w to high takes place on TCC pin 1 : increment if the transition from high to low takes place on TCC pin Bit 3 (PAB): Prescaler Assigned Bit 0 : TCC 1 : WDT Bit 2 Bit 0 (PSR2 PSR0) TCC/WDT prescaler bits PSR2 PSR1 PSR0 TCC Rate WDT Rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0
46、1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 The CONT register is both readable and writable. FAE: 135 9015 2895EM78P152/3S 8-Bit Microcontroller with OTP ROM 10 Product Specification (V1.7) 01.12.2009 (This specification is subject to change without further notice) 5.2.3 IOC5 IOC6 (
47、I/O Port Control Register) 0 : defines the relative I/O pin as output 1 : puts the relative I/O pin into high impedance Only the lower 4 bits of IOC5 are available to be defined. IOC5 and IOC6 registers are both readable and writable. 5.2.4 IOCB (Pull-down Control Register) Bit 7 Bit 6 Bit 5 Bit 4 B
48、it 3 Bit 2 Bit 1 Bit 0 - /PD6 /PD5 /PD4 - /PD2 /PD1 /PD0 Bit 7: Not used 0 : Enable internal pull-down 1 : Disable internal pull-down Bit 6 (/PD6): Control bit used to enable pull-down of the P62 pin. Bit 5 (/PD5): Control bit used to enable pull-down of the P61 pin. Bit 4 (/PD4): Control bit used t
49、o enable pull-down of the P60 pin. Bit 3: Not used Bit 2 (/PD2): Control bit used to enable pull-down of the P52 pin. Bit 1 (/PD1): Control bit used to enable pull-down of the P51 pin. Bit 0 (/PD0): Control bit used to enable pull-down of the P50 pin. The IOCB Register is both readable and writable. 5.2.5 IOCC (Open-drain Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B
