1、- 09 091150022 - _405 43 2010.12.19 -11. 2. 4(74ls181) 2-1-174181/8alu-(74245)(74373)input device-(74245)bus unit1-2()t4w/r unitw/r unitt4state unitkk2s3s2s1s0cnlddr1lddr2alu-bsw-bswitch unitcnalu-bsw-blddr1lddr2-3zye1603b- 41. 1-2 2.dr1dr210dr111000001c1hdr20100001143hclr=1,lddr1=0,lddr2=0.alu_g=1,
2、 sw_g=1,s3 s2 s1 s0 m cn=111111,sp05normsp03stepsp04runt4startt4:sp03stepsp04runstartt4dr1dr2sw_g=1alualu_g=0alus3s2s1s0mcn111111data busdr1101011data busdr23. 74ls181-74ls1811-1s3 s2 s1 s0 m cnab+-1-1 74ls181-dr1c1hdr243ha=c1hb=43hs3 s2 s1 s0 m cn1-274ls1815674ls181 7-74181alu-alu 1201 1208030113 2
3、014-11-201. -alu2. -verilog3. modelsimquartus2pc4. -alu-alualu-alu-1alu1 alu-alu-alu-aluverilogmodule alu181a(s,a,b,f,m,cn,co,fz); input3:0 s; input7:0 a,b; input m,cn; output7:0 f; output co,fz; wire7:0 f; wire co;wire8:0 a9,b9; reg fz; reg8:0 f9; assign a9=1b0,a; assign b9=1b0,b;always (m or cn or
4、 a9 or b9 or s) begin case(s)4b0000: if(m=0) f9=a9+cn; else f9=a9; 4b0001: if(m=0) f9=(a9|b9)+cn; else f9=(a9)b9;4b0010: if(m=0) f9=(a9|(b9)+cn; else f9=a9;4b0011: if(m=0) f9=9b000000000-cn; else f9=9b000000000;4b0100: if(m=0) f9=a9+(a9b9)+cn; else f9=(a9b9);4b0101: if(m=0) f9=(a9+b9)+(a9b9)+cn); el
5、se f9=b9; 4b0110: f9=a9b9;4b0111: if(m=0) f9=a9+(b9)-cn; else f9=a9(b9);4b1000: if(m=0) f9=a9+(a9b9)+cn; else f9=(a9)+b9; 4b1001:if(m=0)f9=a9+b9+cn;elsef9=(a9b9);4b1010: if(m=0) f9=a9+(b9)+(a9b9)+cn; else f9=b9;4b1011: if(m=0) f9=(a9b9)+cn; else f9=(a9b9); 4b1100:if(m=0)f9=a9+a9+cn;elsef9=9b00000000
6、1;if(m=0)f9=a9-b9-cn;else- 113030102 11303010221 18182204274 1 2 13312 11303010234 3. 11. 2. 4(74ls181) 2-1-174181/8alu-(74245)(74373)input device-(74245)bus unit1-2()t4w/r unitw/r unitt4state unitkk2s3s2s1s0cnlddr1lddr2alu-bsw-bswitch unitcnalu-bsw-blddr1lddr23zye1603b- 41. 2. dr1dr210dr111000001c1
7、hdr20100001143hclr=1,lddr1=0,lddr2=0.alu_g=1, sw_g=1,s3 s2 s1 s0 m cn=111111,sp05normsp03stepsp04runt4startt4:sp03stepsp04runstartt4dr1dr2sw_g=1alualu_g=0alus3s2s1s0mcn111111data busdr1101011data busdr23. 74ls181-74ls1811-1s3 s2 s1 s0 m cnab+-1-1 74ls181 2015-11-11. 2. -2.1. -abab(-arm)s3?s0cnalufc,
8、alualucpld- -0. - 0-cpldalu74ls245cpufct4clralut1t2t3t4t1t2t3t4clrconclrt4ts4,cont4alu_b-abled-fcfzd7?d0-alu-s3s2s1s0cnfcfzfcfz (-)pcstkk2st4.1 ab-alu_b=0lda=0,ldb=0s3s2s1s0=0010alu_b=0lda=0,ldb=0s3s2s1s0=0011a+b-? ? ? ? in()addstarr(), rrc()rl()rlc()set11011. 1. 2-3 4. 5. 6. 74299 74181 alumcn-s3s2s1s0 -dr1dr2r0pc arir: raminput: k7k0 output:2. 103. - 21set -set 331-3145 346474701s3s2s1s0 alum m=1 alu-m=0 alu cn: wew/r ram out a9a8ramoutputinput a9a8=00 input swb a9a8=01 ram ce a9a8=10 output ledba9a8=11 3a b cab c
