1、QuadSPIMicrocontrollers DivisionApplication TeamIntroduction02/07/201519QUADSPIOverview Communication interface for single/dual/quad SPI flash memories Three operating modes Indirect : all the operations are performed through registers (classical SPI) Statuspolling : periodical read of the flash sta
2、tus registers (interrruptgeneration) Memorymapped : External flash seen as internal for read operations20Registers/ ControlClockManagementShift RegisterFIFOQSPI FlashCLKBK1_IO0/SOBK1_IO1/SIBK1_IO2BK1_IO3BK1_nCSAHB CLKQ0/SIQ1/SOQ2/nWPQ3/nHOLDnCSDual-quad mode Access two flashes in parrallel with the
3、same frame format and the same instruction (8-bit par cycle)21QUADSPIRegisters/ ControlClockManagementShift RegisterFIFOQSPI FlashCLKBK1_IO0/SOBK1_IO1/SIBK1_IO2BK1_IO3BK1_nCSAHB CLKQ0/SIQ1/SOQ2/nWPQ3/nHOLDnCSQSPI FlashBK2_IO0/SOBK2_IO1/SIBK2_IO2BK2_IO3BK2_nCSCLKQ0/SIQ1/SOQ2/nWPQ3/nHOLDnCSMain featur
4、es Three functional modes: Indirect Status-polling Memory-mapped Optimized operations SDR and DDR support Fully programmable Opcode for both indirect and memory mapped mode Frame format for both indirect and memory mapped mode Integrated FIFO for reception and transmission 8, 16, and 32-bit data acc
5、esses are allowed DMA channel for indirect mode operations Interrupt generation on FIFO threshold, timeout, operation complete, and access error22Frame format Each of the 5 phases is fully configurable Enabled or not Lenght Number of lanes Exemple of Read configuration Instruction on 1 lane Address,
6、 Alternate & Data on 4 lanes 2 dummy cycles23nCSSCLKIO0IO1IO2IO3456701234567012345670123456701234567012345670123A23-16 A15-8 A7-0 M7-0 Byte 1 Byte 2Instruction Address Alt Dummy DataIO switch from output to input7 6 5 4 3 2 1 0Indirect mode Same usage as a classical communication IP The data are tra
7、nsferred writing or reading data register Number of bytes specified in the datalenght register Management of data FIFO with Interrupts flag (Transfer Complete Flag) DMA support Launching a command When writing the instruction if only instruction is needed When writing the address if only instruction
8、 & address are needed When writing the data when data phase are needed24Status polling mode Specific mode for polling a Status Register Programmable register lenght : 8/16/24/32-bit Repeat the read operation at a defined rate Mask the response and generate an interrupt in case of match Programmable
9、mask (PSMKR register) The masked value is compared bit per bit with the match register (PSMAR) The result of the comparison can be ANDed or ORed. Interrupt is generated when succeed (Stop on Match Flag) Automatic stop When a match occurs the QuadSPI can stop itself automatically25Memory-mapped mode
10、For read operation only External flash is seen as internal with wait states Read operations are automatically generated on AHB access Frame & opcode defined during IP configuration as for indirect mode Prefetch for XiP nCS is held low and clock is stopped to stall the QuadSPI bus and relaunch sequen
11、tial read if needed Timeout counter to release nCS High for low power26Delay data sampling The sampling clock can be shifted by additional 0,5 cycle Usefull for signal delay on the PCB Clock shifting not supported in DDR mode27Summary QuadSPI flash support Fully programmable and configurable Shall s
12、upport all the QuadSPI flashes in the market Shall support new command without any HW modifications Specific mode for Status register polling without CPU Easy integration in existing firmware thanks to memory mapped mode28Programmer Model02/07/201529Overview Configuration IP configuration External f
13、lash parameter configuration Low-power timeout functionality is needed Communication initialisation Alternate bytes value The number of data to be transfered in indirect The automatic polling mode configuration if used The frame format configuration Communication starts When writing the instruction
14、if only instruction is needed (or in memory-mapped mode) When writing the address if only instruction & address are needed When writing the data in write mode when data phase are needed02/07/201530Control register Defines the functional mode of the QUADSPICan be changed only when BUSY bit is 0 (exce
15、pt ABORT bit)02/07/201531Name Size DescriptionPRESCALER 8 bits Scaling factor for the generated clock AHB.FCLK can be in the range FAHB down to FAHB/255.PMM 1 bit Bits are ANDed or ORed to generate the match eventAPMS 1 bit Automatic polling stops when a match occursFTHRES 4 bits Defines the FIFO Th
16、reshold level to set the FIFO Threshold flag (indirect mode)SSHIFT 1 bit Shift the sampling data of half a clock cycle (only in SDR)TCEN 1 bit Timeout counter enableDMAEN 1 bit DMA request generation enableABORT 1 bit Abort the ongoing sequenceEN 1 bit Enable the QUADSPIDevice configuration register
17、02/07/201532Name Size DescriptionFSIZE 5 bit Size of the Flash = 2FSIZE+1CSHT 3 bit Chip Select High Time in number of clock cyclesCKMODE 1 bit Select between SPI mode 0 and mode 3 Define the configuration of the external flashTimeout After each access in memory-mapped mode, the QUADSPI prefetches t
18、he subsequent bytes and holds these bytes in the FIFO When the FIFO is full, the communication clock is stopped but the nCS pin remains low to keep the flash selected and not resend a complete command to read the next bytes when location will be available in the FIFO To avoid extra power consumption
19、 in the external flash when the clock is stop for a long time, the timeout counter can release the nCS pin to put the external flash in a lower-consumption state. The timeout value is programmed in the QUADSPI low-power timeout register The timer is enabled setting the TCEN bit in the QUADSPI contro
20、l register02/07/201533Reminder Each of the 5 phases is fully configurable through the QUADSPI communication register Enabled or not Lenght Number of lanes Exemple of Read configuration Instruction on 1 lane Address, Alternate & Data on 4 lanes 2 dummy cycles02/07/201534nCSSCLKIO0IO1IO2IO345670123456
21、7012345670123456701234567012345670123A23-16 A15-8 A7-0 M7-0 Byte 1 Byte 2Instruction Address Alt Dummy DataIO switch from output to input7 6 5 4 3 2 1 0Communication configuration register1/3 Programmed in the QUADSPI communication configuration register (BUSY bit is 0)02/07/201535Name Size Descript
22、ionDDRM 1 bit Double Data Rate ModeSIOO 1 bit Send instruction only onceFMODE 2 bits Select the functional mode for the instruction00: Indirect write mode01: Indirect read mode10: Automatic polling mode11: Memory-mapped modeDMODE 2 bits Defines the data phase mode of operation00: No data01: Data on
23、a single line10: Data on two lines11: Data on four linesDCYC 5 bits Defines the number of the dummy cycles from 0 to 31Communication configuration register2/302/07/201536Name Size DescriptionABSIZE 2 bits Defines the alternate byte size00: 8-bit alternate byte01: 16-bit alternate bytes10: 24-bit alt
24、ernate bytes11: 32-bit alternate bytesABMODE 2 bits Defines the alternate byte mode00: No alternate byte 01: Alternate byte on a single line10: Alternate byte on two lines11: Alternate byte on four linesADSIZE 2 bits Defines the address size00: 8-bit address 01: 16-bit address 10: 24-bit address 11:
25、 32-bit address bytesADMODE 2 bits Defines the address mode00: No address 01: Address on a single line10: Address on two lines11: Address on four linesCommunication configuration register3/3 In indirect mode and in automatic polling mode the address, when needed, is programmed in the QUADSPI address
26、 register When needed, the alternate byte value are programmed in the QUADSPI alternatebytes register In indirect mode the number of data is programmed in the QUADSPI data length register In indirect mode the data are read/write through the QUADSPI data register02/07/201537Name Size DescriptionIMODE
27、 2 bits Defines the instruction mode00: No instruction 01: Instruction on a single line10: Instruction on two lines11: Instruction on four linesINSTRUCTION 8 bits Instruction to be send to the external QUADSPI FlashAutomatic polling mode In automatic polling mode, the QuadSPI retrievesautomatically
28、a 8-bit up to 32-bit value in the flash The value is masked according to the QUADSPI polling statusmask register The masked result is compared with the content of the QUADSPI polling statusmatch register Depending on the mode (AND or OR) selected by the PMM bit of the QUADSPI control register, the c
29、omparison result bits are ANDed or ORed to generatethe match event setting the SMF bit of the QUADSPI statusregister.02/07/201538Interrupts02/07/201539Interrupt Flag Enable Clear DescriptionTimeout TOF TOIE CTOF Timeout occuredStatusMatch SMF SMIE CSMF Matching of the masked received data with the m
30、atch register (automatic polling mode only)FIFO Threshold FTF FTIE - FIFO Threshold reached (indirect mode).TranferComplete TCF TCIE CTCFThe correct number of data has beentransferred (indirect mode) or the transfer has been aborted (all modes)TranferError TEF TEIE CTEF Out of range address has been
31、 accessed (indirect mode)Additional status bits Additional flags are available in the QUADSPI Status Register to easethe software integration FIFO Level Busy bit02/07/201540Name Size DescriptionFLEVEL 5 bit Number of valid bytes being held in the FIFO (only for indirect mode)BUSY 1 bit This bit is s
32、et when an operation is on going. Clears automatically when operations are finished and FIFO is empty.Summary Configuration Steps IP configuration through the QUADSPI control register External flash configuration through the QUADSPI deviceconfiguration register Low-power timeout duration is programm
33、ed in the QUADSPI low-power timeout register Communication initialization Alternate bytes, when needed, are programmed in the QUADSPI alternatebytes register The number of data to be transfered in indirect mode is programmed in the QUADSPI data lenghtregister The automatic polling mode configuration
34、 is defined through the QUADSPI polling status maskregister, the QUADSPI polling statusmatch register and the QUADSPI polling intervalregister The frame format is configured through the QUADSPI communication configuration register Communication starts When writing the QUADSPI communication configuration register if only instruction is needed (or in memory-mapped mode) When writing the QUADSPI addressregister if only instruction & address are needed When writing the QUADSPI data register in write mode when data phase are needed02/07/201541
