1、DS748 July 25, 2012 1Product Specification Copyright 20102012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA and ARM are trademarks of ARM in
2、 the EU and other countries. All other trademarks are the property of their respective owners. IntroductionThe AXI Universal Asynchronous Receiver Transmitter(UART) 16550 connects to the AMBA(AdvanceMicrocontroller Bus Architecture) AXI (AdvancedeXtensible Interface) and provides the controllerinter
3、face for asynchronous serial data transfer. This softIP core is designed to connect through an AXI4-Liteinterface.The AXI UART 16550 described in this documentincorporates features described in the NationalSemiconductor PC16550D UART with FIFOs Data Sheet.The National Semiconductor PC16550D data she
4、et isreferenced throughout this document and should beused as the authoritative specification. Differencesbetween the National Semiconductor PC16550D andthe AXI UART 16550 data sheet are highlighted in theSpecification Exceptions section.FeaturesAXI interface is based on AXI4-Lite specificationHardw
5、are and software register compatible with all standard 16450 and 16550 UARTsSupports default core configuration for 9600 baud, 8 bits data length, 1 stop bit and no parityImplements all standard serial interface protocols5, 6, 7 or 8 bits per characterOdd, Even or no parity detection and generation1
6、, 1.5 or 2 stop bit detection and generationInternal baud rate generator and separate receiver clock inputModem control functionsPrioritized transmit, receive, line status and modem control interruptsFalse start bit detection and recoverLine break detection and generationInternal loopback diagnostic
7、 functionality16 character transmit and receive FIFOsLogiCORE IP AXI UART 16550(v1.01a)DS748 July 25, 2012 Product SpecificationLogiCORE IP Facts TableCore SpecificsSupported Device Family(1)Zynq-7000(2), Virtex-7, Kintex-7,Artix-7,Virtex-6, Spartan-6Supported User InterfacesAXI4-LiteResources See T
8、able 18, Table 19, Table 20, Table 21,Table 22Provided with CoreDesign Files VHDLExample Design Not ProvidedTest Bench Not ProvidedConstraints File Not ProvidedSimulation ModelN/ASupported S/W Driver(3)Standalone and LinuxTested Design Flows(4)Design EntryXilinx Platform Studio (XPS)Vivado Design Su
9、ite(5)Simulation Mentor Graphics ModelSimSynthesisXilinx Synthesis Technology (XST)Vivado SynthesisSupportProvided by Xilinx For a complete list of supported derivative devices, see the Embedded Edition Derivative Device Support.2. Supported in ISE Design Suite implementations only.3. Standalone dr
10、iver details can be found in the EDK or SDK directory (/doc/usenglish/xilinx_drivers.htm). Linux OS and driver support information is available from /.4. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide5. Supports only 7 series devices.DS748 July 25, 2012 2P
11、roduct SpecificationLogiCORE IP AXI UART 16550 (v1.01a)Functional DescriptionThe AXI UART 16550 implements the hardware and software functionality of the National Semiconductor 16550UART, which works in both the 16450 and 16550 UART modes. For complete details, see the NationalSemiconductor data she
12、et.The AXI UART 16550 performs parallel to serial conversion on characters received from the AXI master and serialto parallel conversion on characters received from a modem or serial peripheral. The AXI UART 16550 is capable of transmitting and receiving 8, 7, 6, or 5 bit characters, with 2, 1.5 or
13、1 stop bits andodd, even or no parity. The AXI UART 16550 can transmit and receive independently. The device can be configured and its status monitored by the internal register set. The AXI UART 16550 is capableof signaling receiver, transmitter and modem control interrupts. These interrupts can be
14、masked, are prioritizedand can be identified by reading an internal register. The device contains a 16-bit, programmable, baud rate generator, and independent 16 character length transmit andreceive FIFOs. The FIFOs can be enabled or disabled through software control.The top-level block diagram for
15、the AXI UART 16550 is shown in Figure 1.The top level modules of the AXI UART 16550 are:AXI Interface ModuleIPIC_IFUART16550The detailed block diagram for the AXI UART 16550 is shown in Figure 2.X-Ref Target - Figure 1Figure 1: Top-level Diagram!8) ,ITE!8)NTERFACE-ODULE)0)#?)=)0“US?)NTR%VENT)0“US?$A
16、TA;=“US)0?#LK“US)0?2ESET-ODEM,OGIC5!248IN8OUT#TS.$CD.$SR.2I.$TR.2TS./UT./UT.$DIS2XRDY.2CLK3IN3OUT4XRDY.,#2,32)%2)2-#2-323#2$,$,-“AUDENERATOR2ECEIVER“AUDOUT.)0).4#?)RPT an overrun interrupt is generated only when FIFO is full and the next character is completely received in the shift register. Parity
17、 Error - This interrupt is generated when the receive character has an invalid parity bit. Framing Error - This interrupt is generated if the received character has an invalid stop bit.Line Break - This interrupt is generated when the Receiver detects logic 0 for longer than a full word transmission
18、 time.The Receiver Line Status Interrupt is cleared by reading the LSR register.Received data available The Received data available interrupt is generated when the Receiver FIFO trigger level is reached. This interruptis cleared when the Receiver FIFO drops below the trigger level.Character Timeout
19、The Character Timeout interrupt is generated when no character has been removed from, or input to, the receiverFIFO during the last 4 character time and there is at least one character in the FIFO during this time. The charactertime considered for timeout (Start + 8 bit data + Parity + 2 Stop bit) i
20、s constant for all configurations. This interruptis cleared by reading Receiver Buffer Register.Transmitter holding register empty The Transmitter holding register empty interrupt is generated when the character is transferred from theTransmitter holding register to the Transmitter shift register. I
21、n the FIFO mode, this interrupt is generated whenTransmitter FIFO becomes empty. This interrupt is cleared by reading the IIR or writing into the Transmitterholding register.Modem Status This interrupt is generated for these modem status conditions:Clear to send Data Set ReadyRing IndicatorData Carr
22、ier DetectThis interrupt is cleared by reading the Modem Status Register.DS748 July 25, 2012 5Product SpecificationLogiCORE IP AXI UART 16550 (v1.01a)I/O SignalsThe I/O signals are listed and described in Table 1.Table 1: I/O Signals Port Signal Name Interface I/OInitial StateDescriptionSystem Sign
23、alsP1 S_AXI_ACLK System I - AXI ClockP2 S_AXI_ARESETN System I - AXI Reset signal, active-LowP3 IP2INTC_Irpt System O 0Device interrupt output to microprocessor interrupt input or system interrupt controller (active-High)P4 Freeze System I - Freezes UART for software debug (active-High)AXI Write Add
24、ress Channel SignalsP5S_AXI_AWADDRC_S_AXI_ADDR_WIDTH-1:0AXI I -AXI Write address. The write address bus gives the address of the write transaction.P6 S_AXI_AWVALID AXI I -Write address valid. This signal indicates that valid write address is available.P7 S_AXI_AWREADY AXI O 0Write address ready. Thi
25、s signal indicates that the slave is ready to accept an address.AXI Write Channel SignalsP8S_AXI_WDATAC_S_AXI_DATA_WIDTH - 1: 0AXI I - Write dataP9S_AXI_WSTBC_S_AXI_DATA_WIDTH/8-1:0 (1)AXI I -Write strobes. This signal indicates which byte lanes to update in memory.P10 S_AXI_WVALID AXI I -Write vali
26、d. This signal indicates that valid write data and strobes are available.P11 S_AXI_WREADY AXI O 0Write ready. This signal indicates that the slave can accept the write data.AXI Write Response Channel SignalsP12 S_AXI_BRESP1:0(2)AXI O 0Write response. This signal indicates the status of the write tra
27、nsaction.“00“ - OKAY“10“ - SLVERRP13 S_AXI_BVALID AXI O 0Write response valid. This signal indicates that a valid write response is available.P14 S_AXI_BREADY AXI I -Response ready. This signal indicates that the master can accept the response information.AXI Read Address Channel SignalsP15S_AXI_ARA
28、DDRC_S_AXI_ADDR_WIDTH -1:0AXI I -Read address. The read address bus gives the address of a read transaction.P16 S_AXI_ARVALID AXI I -Read address valid. When High, this signal indicates that the read address is valid and remains stable until the address acknowledgement signal, S_AXI_ARREADY, is High
29、.P17 S_AXI_ARREADY AXI O 1Read address ready. This signal indicates that the slave is ready to accept an address.DS748 July 25, 2012 6Product SpecificationLogiCORE IP AXI UART 16550 (v1.01a)AXI Read Data Channel SignalsP18S_AXI_RDATAC_S_AXI_DATA_WIDTH -1:0AXI O 0 Read dataP19 S_AXI_RRESP1:0(2)AXI O
30、 0Read response. This signal indicates the status of the read transfer.“00“ - OKAY“10“ - SLVERRP20 S_AXI_RVALID AXI O 0Read valid. This signal indicates that the required read data is available and the read transfer can completeP21 S_AXI_RREADY AXI I -Read ready. This signal indicates that the maste
31、r can accept the read data and response informationUART Interface SignalsP22 BaudoutN Serial O 1 16 x clock signal from the transmitter section of the UARTP23 Rclk Serial I -Receiver 16x clock (Optional, can be driven externally under control of the C_HAS_EXTERNAL_RCLK parameter)P24 Sin Serial I - S
32、erial data inputP25 Sout Serial O 1 Serial data outputP26 Xin Serial I -Baud rate generator reference clock (Optional, can be driven externally under control of the C_HAS_EXTERNAL_XIN parameter)P27 Xout Serial O 0If C_HAS_EXTERNAL_XIN = 0, Xout is 0, if C_HAS_EXTERNAL_XIN = 1 Xout can be used as ref
33、erence feedback clock for Baud rate generator P28 CtsN Modem I -Clear to send (active-Low). When Low, this indicates that the MODEM or data set is ready to exchange data. P29 DcdN Modem I -Data carrier detect (active-Low). When Low, indicates that the data carrier has been detected by the MODEM or d
34、ata set.P30 DsrN Modem I -Data set ready (active-Low). When Low, this indicates that the MODEM or data set is ready to establish the communication link with the UART.P31 DtrN Modem O 1Data terminal ready (active-Low). When Low, this informs the MODEM or data set that the UART is ready to establish a
35、 communication link.P32 RiN Modem I -Ring indicator (active-Low).When Low, this indicates that a telephone ringing signal has been received by the MODEM or data set.P33 RtsN Modem O 1Request to send (active-Low). When Low, this informs the MODEM or data set that the UART is ready to exchange data.P3
36、4 Ddis User O 1Driver disable. This goes Low when CPU is reading data from UART. P35 Out1N User O 1 User controlled outputP36 Our2N User O 1 User controlled outputTable 1: I/O Signals (Contd)Port Signal Name Interface I/OInitial StateDescriptionDS748 July 25, 2012 7Product SpecificationLogiCORE IP
37、AXI UART 16550 (v1.01a)Design ParametersTo allow the user to create an AXI UART 16550 that is uniquely tailored for the users system, certain features areparameterizable in the AXI UART 16550 design. This allows the user to have a design that utilizes only theresources required by the system and run
38、s at the highest possible performance. The parameterizable features in theAXI UART 16550 core are as shown in Table 2.In addition to the parameters listed in this table, there are also parameters that are inferred for each AXI interface inthe EDK tools. Through the design, these EDK-inferred paramet
39、ers control the behavior of the AXI Interconnect.For a complete list of the interconnect settings related to the AXI interface, see DS768, AXI Interconnect IP Data Sheet. P37 RxrdyN User O 1 DMA control signalP38 TxrdyN User O 0 DMA control signalNotes: 1. This signal is not used. The AXI UART 16550
40、 assumes that all byte lanes are active.2. For these signals, the IP core does not generate the Decode Error (“11”) response. Other responses such as “00” (OKAY) and “10” (SLVERR) are generated by the core based on certain conditions. Table 2: Design Parameters Generic Parameter Description Paramete
41、r Name Allowable Values Default ValueVHDL TypeSystem ParametersG1 Target FPGA family C_FAMILYvirtex7, kintex7, artix7, zynq, virtex6,spartan6virtex6 stringG2System clock frequency (in Hz) driving the 16550 UART peripheralC_S_AXI_ACLK_FREQ_HZinteger (ex.100000000)100_000_000integerAXI ParametersG3 AX
42、I address bus width C_S_AXI_ADDR_WIDTH 13 13 integerG4 AXI data bus width C_S_AXI_DATA_WIDTH 32 32 integer16550 UART InterfaceG5 External xin clock C_HAS_EXTERNAL_XIN 0: xin is open(1)(2)1: xin is externally driven0 integerG6 External Receiver clock C_HAS_EXTERNAL_RCLK0 : rclk is open1 : rclk is ext
43、ernally driven0 integerG7 Select 16450/16550 UART C_IS_A_165500 : 16450 mode1 : 16550 mode1 integerTable 1: I/O Signals (Contd)Port Signal Name Interface I/OInitial StateDescriptionDS748 July 25, 2012 8Product SpecificationLogiCORE IP AXI UART 16550 (v1.01a)Parameter - Port DependenciesThe dependen
44、cies between the AXI UART 16550 core design parameters and I/O signals are described in Table 3.In addition, when certain features are parameterized out of the design, the related logic is no longer a part of thedesign. The unused input signals and related output signals are set to a specified value
45、.G8External xin clock frequency in Hz.C_EXTERNAL_XIN_CLK_HZ(3)Valid xin clock frequency in Hz.25000000 integerNotes: 1. When C_HAS_EXTERNAL_XIN=0, this core uses S_AXI_ACLK as a reference clock for the baud calculation. User must use S_AXI_ACLK frequency to calculate baud divisor value for DLL and D
46、LM register configuration.2. The external xin input clock must be less than half of S_AXI_ACLK. 3. External xin clock frequency. User must configure this parameter when external xin is used. (C_HAS_EXTERNAL_XIN is 1).Table 3: Parameter-Port Dependencies Generic or PortName Affects Depends Relationsh
47、ip DescriptionDesign ParametersG3 C_S_AXI_ADDR_WIDTH P5, P15 - Defines the width of the portsG4 C_S_AXI_DATA_WIDTHP8, P9, P18- Defines the width of the portsI/O SignalsP5S_AXI_AWADDRC_S_AXI_ADDR_WIDTH-1:0-G3Port width depends on the generic C_S_AXI_ADDR_WIDTHP8S_AXI_WDATAC_S_AXI_DATA_WIDTH-1:0-G4Por
48、t width depends on the generic C_S_AXI_DATA_WIDTHP9S_AXI_WSTBC_S_AXI_DATA_WIDTH/8-1:0-G4Port width depends on the generic C_S_AXI_DATA_WIDTHP15S_AXI_ARADDRC_S_AXI_ADDR_WIDTH -1:0-G3Port width depends on the generic C_S_AXI_ADDR_WIDTHP18S_AXI_RDATAC_S_AXI_DATA_WIDTH -1:0-G4Port width depends on the generic C_S_AXI_DATA_WIDTHP23 Rclk - G6If C_HAS_EXTERNAL_RCLK = 0 baudoutN is used as 16x receiver clock, C_HAS_EXTERNAL_RCLK = 1, rclk is used as 16x receiv
