1、 1AN-1087 Application Note AN-1087 Design of Secondary Side Rectification using IR1167 SmartRectifier Control IC By Maurizio Salato, Adnaan Lokhandwala, Marco Soldano Table of Contents Device Overview SmartRectifier Concept Operation and analysis in CCM hence, an externally programmable Minimum On
2、Time (MOT) blanking period is used that will maintain the power MOSFET on for a minimum amount of time. The programmed MOT will limit also the minimum duty cycle of the SR MOSFET and, as a consequence, the max duty cycle of the primary side switch. Figure 4: MOT and tBLANKduring operation in DCM. No
3、tice both Minimum On Time and Blanking time logic are allowed only once per switching cycle; it is necessary that VDSreaches VTH3(therefore primary turn on) for them being enabled again (therefore ready for the next switching cycle). 5AN-1087 DCM/CrCM Turn Off Phase Once the SR MOSFET has been turn
4、ed on, it will remain on until the rectified current will decay to the level where VDSwill cross the turn-off threshold VTH1. This will happen differently depending on the mode of operation. In DCM the current will cross the threshold with a relatively low dtdI. Once the threshold is crossed, the cu
5、rrent will once again flow through the body diode, causing the VDSvoltage to jump negative. Depending on the amount of residual current, VDSmay again trigger the turn on threshold: for this reason VTH2is blanked for an internally set blank time tblank (as shown in Figure 4) after VTH1has triggered.
6、As soon as VDScrosses the positive threshold VTH3, this blanking time is terminated and the IC is ready for next conduction cycle. ID_PRIMID_SECVDS_SECVDS_PRIMtimetimeT1 T2T3Figure 5: DCM operating flyback converter simplified waveforms. 6AN-1087 timetimeT1T2ID_PRIMID_SECVDS_SECVDS_PRIMFigure 6: Cr
7、CM operating flyback converter simplified waveforms. CCM Turn Off Phase During the SR FET conduction phase the current will decay linearly, and so will VDSon the SR FET. Once the primary switch will start to turn back on, the SR FET current will rapidly decrease crossing VTH1and turning the gate off
8、. The turn off speed is more critical here to avoid cross conduction on the primary side and reduce switching losses. The blanking period is also applied in this case, but given the very fast nature of this transition, it will be reset as soon as VDScrosses VTH3. timetimeT1T2ID_PRIMID_SECVDS_SECVDS_
9、PRIMFigure 7: CCM operating flyback converter simplified waveforms. 7AN-1087 Operation in Resonant Converters Figure 8 shows the typical secondary-side schematic for a series resonant converter with a capacitive output filter. Implementing synchronous rectification in such applications would requir
10、e 2 current sense transformers, 2 high speed comparators and finally 2 high current, low propagation delay gate drivers needed to drive the two power devices. Existing monolithic solutions are based on PLL control techniques and rely on synchronizing signals from the primary-side to anticipate the t
11、urn off transition for the secondary MOSFETs; hence, they cannot guarantee reliable operation when the converter operates in burst mode during light and no load conditions. The SmartRectifier control technique operates completely independent of the primary-side switching technique and the low dtdItr
12、ansitions in the resonant converter make the IR1167 an excellent candidate in such applications. Figure 9 illustrates this with waveforms. LpLs1Ls2Cout LOADM1M2Figure 8: Series resonant converter secondary-side general schematic. IR1167 operates completely independent of the primary-side switching t
13、echnique and the low dtdItransitions make it an excellent candidate for such applications as shown in Figure 9 below. 8AN-1087 Gate DriveID_SECVDS_SECBlankingtimetimeT1 T2VTH1VTH2VTH3MOT tblankFigure 9: Series resonant converter with IR1167 SmartRectifier control IC general waveforms. In resonant c
14、onverter applications, output voltage regulation can be achieved by operating in fixed or variable frequency (50% duty cycle) operating modes. In variable frequency applications, the converter operates at the minimum switching frequency at low line-full load conditions and at the maximum frequency a
15、t high line-no load conditions. Hence, the MOT selection for resonant converters can simply be based on the maximum switching frequency of the converter. MOT ensures proper gating signals for the synchronous MOSFETs during light load conditions (i.e. operating at maximum switching frequency), and th
16、e situation only improves when the converter operates at heavier loads. Typical System Schematics and Passive Components Nomenclature Passive components needed for IR1167 operations are: C: supply decoupling capacitor Rg: synchronous MOSFET gate resistor RMOT: Minimum On Time setting resistor Compon
17、ent not necessary but recommended: RCC: series resistor on supply In all the low side configurations, power can be drawn directly from converters output whenever its regulated voltage falls in the recommended range (12-20V). In all other cases, recommendation is to provide a dedicated supply through
18、: 9AN-1087 Auxiliary transformer winding if high side Transformer main winding tap if low side Figure 10 to Figure 16 show typical systems schematics. +-OUTPUTCVccOVTMOTENVdVsGNDVgateIR1167RRmotRgFigure 10: single ended, low side rectification, supply from winding tap (VoutputWhere Cissis the switc
19、h input capacitance (from switch datasheet). Figure 21 shows how this critical resistance value varies with the overall gate loop inductance for some popular International Rectifier MOSFETs. IR1167 driving stage: minimum required gate resistor vs. gate loop inductance for circuit damping using some
20、popular IR HexFET (0.7 IR1167 driver impedance and 1.2 FET internal gate resistance included)0123456785 8 11 14 17 20 23 26 29 32 35Total gate loop inductance nHCriticalgate resistanceforloop damping IRF7853 Ciss = 1.64nFIRF6644 Ciss = 2.21nFIRFB4610 Ciss = 3.55nFIRFB4410 Ciss = 5.15nFIRFB4110 Ciss
21、= 9.62nFFigure 21: minimum external gate resistor vs. gate loop inductance for some MOSFETs. It is evident how a good layout practice can dramatically reduce this requirement. 19AN-1087 Now, lets consider the well known series RC network transient: the energy dissipated by the resistor is exactly e
22、qual to the energy stored in the capacitor. IR1167S internal gate driver is of course always in series with the external gate resistor, which means they will linearly share the power dissipation. First, lets calculate the energy stored in the MOSFET gate: 221highgsyncgVCE = The power dissipated by t
23、he driver buffer AND the total gate resistance will therefore be gSWdrEfPmax2= The driver buffer and the total gate resistance will linearly share this power dissipation as described in the following relationship: 2drSinkggSourceggRPRRRRRRPg+= Rearranging this last relationship +=SinkggSourceggdrRRR
24、RRRRPPg21and solving it with respect to Rg(which includes the external gate resistor and the MOSFET internal gate resistance), it is possible to plot the percentage of the total driving power dissipated into the gate resistor as a function of its value. This is also useful for proper dimension the g
25、ate resistor itself. Notice on IR1167S datasheet, pull up and pull down resistances are defined; while downSinkrR = , upSourcerR 1.1= in order to account for some extra energy dissipated for voltage clamping. 20AN-1087 IR1167 driving stage: percentage of the required driving power Pdrdissipated in
26、the gate resistor as a function of the gate resistor value0%10%20%30%40%50%60%70%80%90%100%012345678910112131415Gate resistor value Percentage ofPdrdissipatedingateresistorWFigure 22: percentage of gate driver power dissipated in the gate resistor as function of its value. It is evident the asymptot
27、ic nature of the curve (it would require an infinite gate resistor for dissipating all the power in it). The final step is the thermal verification for the chosen value. Using the maximum thermal resistance junction to ambient, the maximum temperature (where ambient refers to the environment in whic
28、h the IC will work , i.e. box, PCB etc.) and the IC maximum junction temperature, it is now possible to calculate the maximum allowable IC power dissipation JAambICJICRTTP_maxmax= where, according to IR1167 datasheet, RJA=128C/W. Because PRgis known and supply current has already been calculated, th
29、is will imply to limit the VCCsupply voltage (therefore the maximum input power for IR1167) CCRICCCIPPVg+= 21AN-1087 Figure 23 shows maximum allowable IR1167A VCCvs. maximum switching frequency for some popular International Rectifier 100V MOSFET, assuming 1 external gate resistor and 85C environmen
30、t IR1167AS maximum VCCvs. synchronous rectifier switching frequencyTIC_J=125C, TIC_amb=85C external RG=1, HexFET 1 gate resistance included1112131415161718192050 100 150 200 250 300 350 400 450 500Maximum synchronous HexFET switching frequency kHzMaximumallowable VCCvoltage VIRF6644 Csynch = 2.4nFIR
31、FB4610 Csynch =5.4nFIRFB4410 Csynch = 7.6nFIRFB4110 Csynch = 10.8nFFigure 23: Max VCCsupply voltage vs. switching frequency for some chosen MOSFET, IR1167AS IC TJ=40C. In order to avoid UVLO issues, VCCdesigns below 12V should be avoided. It is clear how supply voltage and gate resistor play a major
32、 role in the design trade off. In most commercial systems, the minimum gate resistor value for loop damping will satisfy the thermal requirements. If not, the procedure has to be iterated taking the following steps Step 1: decrease the VCCto the lowest possible value through a series resistor: CCCCs
33、upplyCCIVVR= If this allows VCCto comply the thermal limit, then gate resistor value can be kept as designed. 22AN-1087 It is worth mentioning the additional benefit of adding some series resistance to supply: an enhanced filtering effect with local decoupling capacitor. For systems powered from th
34、e output (no dedicated power through windings, etc.) this can result in smoother operations Step 2: increase the gate resistor value. This can be of some effect if a small resistance has been used, according to Figure 22. d. Decoupling capacitor Several techniques are possible for decoupling capacit
35、or sizing, depending upon system topology and or special requirements. As general guideline a capacitor of at least 100nF should be used. The two most common cases are IR1167S powered directly form the output or from a dedicated winding. In the first case, in order to reduce the voltage ripple and p
36、ossible noise, a good criteria is to use a series resistor on supply (if not already used for thermal management reasons) and size the capacitor in order to obtain a low pass filter with pole frequency a couple of octaves below the minimum operating switching frequency (not stand-by) CCSWRfC=min2min
37、Figure 24 chart shows some obtained values as examples. A minimum value of 100nF limits the curves. 23AN-1087 Decoupling capacitor value vs minimum switching frequency (4 RCCvalues) for -10dB attenuation (two octaves on frequency domain) 0.0E+002.0E-074.0E-076.0E-078.0E-071.0E-061.2E-061.4E-061.6E-
38、061.8E-062.0E-0610 60 110 160 210 260Converter minimum operating frequency kHzDecoupling capacitorvalueCRcc = 10ohmRcc = 33ohmRcc = 66ohmRcc = 100ohmFigure 24: decoupling capacitor value vs. min. switching frequency, 10dB attenuation on supply. In case of operations through aux winding or winding ta
39、p, decoupling capacitor should be sized in order to allow one switching period operation even in absence of main supply, within an acceptable voltage ripple VCC CCSWCCVfIC=minmine. MOT resistor Being the MOT setting linear with the resistor value, the following relationship can be used MOTMOTtR10105
40、.2 = 24AN-1087 f. Rectifier turn off maximum current slope calculation for CCM systems In CCM systems, it is highly recommended to control secondary slope turnoffSECdtdIwhen the SmartRectifier turns off, in order to maximize efficiency. Figure 25 shows turn off waveforms, where at given times: t1:
41、primary switch turns on t2: secondary VDShits VTH1threshold t3: secondary VDSand IDreach zero ID_SECVDS_SECtimeVTH1offturnSECdtdISR Gate DrivetDoff+ 3gate offt1t2t3timeFigure 25: SmartRectifier turn off waveforms in dI/dt controlled CCM conditions. It is evident, the optimal condition is to have syn
42、chronous FET turned off when the current approaches zero. In order to obtain this, dtdVDSshould be designed such as enough time is allowed to internal logic to react (tDoffon IR1167 datasheet) and to gate driver to completely discharge the gate (3 times the gate loop time constant at turn off, i.e.
43、syncdowngFETgoffgateCrRR += )( , where resistances are internal MOSFET gate resistance, external gate resistor and driver pull down resistance). This normally ends up to be in the range of 55 100ns. The secondary current slope at turn of should therefore be designed according to 25AN-1087 )3(1offga
44、teDoffonDSTHturnoffSECtRVdtdI+ In order to obtain this, a small saturable core in series with the primary winding could be used or a sufficiently rugged primary transistor with slow turn on for small power systems. The primary maximum current slope requirement at turn on will be easily calculated us
45、ing transformer turns ratio: turnoffSECPRISECturnonPRIdtdINNdtdI= If this design condition is met, the reverse current through the Synchronous FET will be minimal and only needed for charging its output capacitance up to the reverse voltage. Design example with IR1167AS (10.7V gate output voltage) S
46、ystem data: kHzfSW250max= sMOT 2.1= Critical Conduction Mode kHzfSW18min= CTambIC80= Low side rectifier system, output voltage 19V (direct supply from converter output possible) Synchronous MOSFET: IRFB4110, 100V 4.5m max nCQg150= VVgs10= nCQgd43= VVgs10= nFCiss62.9= ; = 3.1FETgR 26AN-1087 a. OVT s
47、etting: ground b. IC current consumption calculation nFVQQCgsgdgsync7.10= ( ) mAfIVCfISWQCCgsyncSWCChigh8.32107maxmax9=+=c. Gate and supply series resistors design and thermal verification Assuming the total gate loop trace length is 15mm (0.6inch) therefore nHLg15 = 5.22issggCLRloopFrom MOSFET data
48、sheet internal gate resistance is 1.3, from IR1167S datasheet driver pull down resistance is 0.7, for a total of 2. It looks therefore reasonable to chose an external gate resistor for the missing part = 5.0gR According to the procedure, lets now verify the system thermally: mWEfPgSWdr3062max= Therefore mWPRRRRRRRRRRPPdrSinkggggSourceggggRRFETFETFETFETFETgg1552_=+=+ Assuming an acceptable IC maximum junction temperature of 130C mWRTTPJAambICJIC390_maxmax= 27AN-1087 Which means a maximum VCCvoltage VIPPPVCCRRICCCFETgg6.16)(_maxmax=+= This value is far away from
