1、TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES,计算机学院,2019/10/21,2,Overview,自动测试生成ATPG (automatic test pattern generation) 算法的改进 九值逻辑 “G-F” 二值表示 “G-F” 二值公式 定理 “G-F” 二值算法 小结,2019/10/21,3,ATPG algorithm improvement,PODEM 算法每次仅向前驱动一步 应该对单门D边界一直驱动 PODEM 算法反向驱赶必须到输入 应该反向驱赶到扇出就进行模拟以验证相容性，这样可以尽早发现不相容 PODEM 算
2、法敏化路径选择最近的输出 应该选择最易观察的输出 PODEM 算法（D算法）要分别搜索单路径和多路经 应该在搜索单路径的同时搜索多路经 ,2019/10/21,4,9-value logic,2019/10/21,5,Sensitization of 5-val and 9-val,或非门敏化条件,2019/10/21,6,Complexity analysis,9值D算法把故障的单路径敏化和多路径敏化统一成了一种形式，从而使5值D算法对m条路经敏化需要2m-1次敏化，降低到m次敏化，极大的降低了算法复杂度。9值运算增加了运算的复杂度。 对“与”/“或”运算，需定义的运算规则，分别为： 5值D
3、算法：52 - C52 = 15 9值D算法： 92 C92 = 45 “G-F”2值算法： 32 C32 = 6,2019/10/21,7,“G-F” two value denotation,y = f ( X ) = f (x1, x2,. xn)正常电路 yG = f ( XG ) = f (x1G, x2G,. xnG)故障电路 yF = f ( XF ) = f (x1F, x2F,. xnF),2019/10/21,8,9-value logic and “G-F” two value denotation,Meaning1/0 0/1 0/0 1/1 X/X 0/X 1/X X
4、/0 X/1,Fault Machine0 1 0 1 X X X 0 1,Good Machine1 0 0 1 X 0 1 X X,5-valuelogic9-value logic,9-valueD D 0 1 X 0/D 1/D 0/D 1/D,“G-F”xiGxiF xiGxiF xiGxiF xiGxiF x xiG xiG xiF xiF,2019/10/21,9,Operation,与、或、非 运算 正常值和故障值分别运算，结果相拼,2019/10/21,10,y = f ( X ) 对任意故障，若有一组输入 X= (x1, x2,. xn) 使得 yGyF = f ( XG
5、)f ( XF ) = f (x1G, x2G,., xnG)f (x1F, x2F,., xnF) = 1 (1-20) 则 X 检测故障。若是输入端 xi上的单固定故障, 则公式(1-20)变为: f (x1,., xi-1, xiG, xi+1,. ,xn)f (x1,. xi-1, xiF xi+1,., xn) = 1.(1-21),“G-F” 2-value formula,2019/10/21,11,公式(1-21)给出了关于故障的完全测试集 f (x1,., xi-1, xiG, xi+1,. ,xn)f (x1,. xi-1, xiF xi+1,., xn) = 1 .(1-
6、21) 公式(1-20)给出了所有可测故障的测试模式和检测这些故障的完全测试集 f (x1G, x2G,., xnG)f (x1F, x2F,., xnF) = 1 . (1-20),Theorem,2019/10/21,12,Example,全加和逻辑（Sum of full-adder） y = x0x1x2 + x0x1x2 + x0x1x2 + x0x1x2 y = x0x1x2 + x0x1x2 + x0x1x2 + x0x1x2,2019/10/21,13,Example,yGyF= yG yF + yG yF= (x0G x1G x2G + x0G x1G x2G + x0G x
7、1G x2G + x0G x1G x2G )( x0F x1F x2F + x0F x1F x2F + x0F x1F x2F + x0F x1F x2F )+ (x0G x1G x2G + x0G x1G x2G + x0G x1G x2G + x0G x1G x2G )( x0F x1F x2F + x0F x1F x2F + x0F x1F x2F + x0F x1F x2F ),输出1-0跳变,输出0-1跳变,2019/10/21,14,Example (cont.),yG yF = x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F +
8、 x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x
9、1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F,2019/10/21,15,Example (cont.),yG yF = x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x
10、2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F + x0G x0F x1G x1F x2G x2F,2019/10/21,16,Fault activity for function block,对功能块的G-F公式f (x1G, x2G,., xnG)f (x1F,
11、x2F,., xnF)进行化简，成为积之和形式针对具体故障选择故障激活立方。例如：全加和的x0:s-a-0故障的激活立方为：x0G x0F x1G x1F x2G x2F= x0G x0F x1 x2 和x0G x0F x1G x1F x2G x2F = x0G x0F x1 x2,2019/10/21,17,Sensitive condition for function block,对功能块的G-F公式f (x1G, x2G,., xnG)f (x1F, x2F,., xnF)进行化简，成为积之和形式针对具体的敏化要求选择敏化条件。例如：全加和的x0:1-0到f:1-0敏化条件为：从 x0
12、G x0F x1G x1F x2G x2F得到 x1 x2 和 x0G x0F x1G x1F x2G x2F得到 x1 x2,2019/10/21,18,Test code equation,测试码方程检测故障功能块中某单故障的完全测试集 m （ 敏化路径上第i个功能块相应的敏化条件的完全集）=1i=1m为某条敏化路径上功能块个数。,2019/10/21,19,“G-F” 2-value algorithm,按路径敏化思想 预处理，写出功能块的积之和形式的布尔表达式 （包括原量和非量） 求功能块测试码 求功能块的敏化条件 建立测试码方程 解方程（即反向回推，并判断相容性）,2019/10/2
13、1,20,Example,求功能块测试码,2019/10/21,21,Example (cont.),建立测试码方程(敏化）,2019/10/21,22,Example (cont.),解方程（相容）,2019/10/21,23,Summary of “G-F” 2-value algorithm,算法是完全的 处理能力等价于9值D算法，比D算法、PODEM算法、FAN算法的效率都高 便于处理复杂的功能块 容易扩展到时序电路 算法运算简单，运算规则少 实践证明算法效率高,2019/10/21,24,Summary of ATPG,ATPG 算法 布尔差分法、一维通路敏化法、D算法、PODEM算
14、法、FAN算法、“G-F”二值算法 算法复杂度 ATPG是NP问题，各种算法复杂度都是O(2n) 算法的发展方向 降低算法复杂度-减小n，但不能降低成多项式复杂度 利用可测性分析指导，在有限时间内收敛或抛弃 利用并行技术加速收敛 组合电路ATPG是测试生成的基础,2019/10/21,25,时序电路测试生成,时序电路自动测试生成 时帧扩展 Example Complexity of ATPG Cycle-free and cyclic circuits 时序电路测试生成系统工作模式 Classification Forward time test generator General comme
15、nts Simulation based test generators 小结,2019/10/21,26,Sequential circuit,含有存储器件或反馈环路的电路 故障状态下可能会引起问题： 无法置初态 竞争冒险 循环振荡,2019/10/21,27,Sequential circuit ATPG,方法 Time-frame expansion methods Forward time, reverse time, forward and reverse time Simulation-based methods,2019/10/21,28,Example: A Serial Ad
16、der,FF,An,Bn,Cn,Cn+1,Sn,s-a-0,1,1,1,1,1,X,X,X,D,D,Combinational logic,2019/10/21,29,Time-Frame Expansion,An,Bn,FF,Cn,Cn+1,1,X,X,Sn,s-a-0,1,1,1,1,D,D,Combinational logic,Sn-1,s-a-0,1,1,1,1,X,D,D,Combinational logic,Cn-1,1,1,D,D,X,An-1,Bn-1,Time-frame -1,Time-frame 0,2019/10/21,30,Concept of Time-Fram
17、es,If the test sequence for a single stuck-at fault contains n vectors, Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic,Comb. block,Fault,Time- frame 0,Time- frame -1,Time- frame -n+1,U
18、nknown or given Init. state,Vector 0,Vector -1,Vector -n+1,PO 0,PO -1,PO -n+1,State variables,Next state,2019/10/21,31,Example for Logic Systems,FF2,FF1,A,B,s-a-1,2019/10/21,32,Five-Valued Logic (Roth) 0,1, D, D, X,A,B,X,X,X,0,s-a-1,D,A,B,X,X,X,0,s-a-1,D,FF1,FF1,FF2,FF2,D,D,Time-frame -1,Time-frame
19、0,2019/10/21,33,Nine-Valued Logic (Muth) 0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X,A,B,X,X,X,0,s-a-1,0/1,A,B,0/X,0/X,0/1,X,s-a-1,X/1,FF1,FF1,FF2,FF2,0/1,X/1,Time-frame -1,Time-frame 0,2019/10/21,34,Complexity of ATPG,同步电路 Synchronous circuit - All flip-flops controlled by clocks; PI and PO synchronized w
20、ith clock: Cycle-free circuit No feedback among flip-flops: Test generation for a fault needs no more than dseq + 1 time-frames, where dseq is the sequential depth. Cyclic circuit Contains feedback among flip-flops: May need 9Nff time-frames, where Nff is the number of flip-flops. 异步电路 Asynchronous
21、circuit Higher complexity!,Time- Frame 0,Time- Frame max-1,Time- Frame max-2,Time- Frame -2,Time- Frame -1,S0,S1,S2,S3,Smax,max = Number of distinct vectors with 9-valued elements = 9Nff,2019/10/21,35,Cycle-Free Circuits,无寄存器之间的反馈环路 时序深度 dseq ：从 PI 到 PO 所经过的最大寄存器数目 正常电路与故障电路都是可初始化的 每个测试序列长度最长不超过 dse
22、q + 1.,2019/10/21,36,Cycle-Free Example,F1,F2,F3,Level = 1,2,3,dseq = 3,s - graph,Circuit,All faults are testable,2019/10/21,37,Cyclic Circuit Example,F1,F2,CNT,Z,反馈时序电路实例：模3计数器（Modulo-3 counter）,s - graph,F1,F2,2019/10/21,38,Modulo-3 Counter,循环结构：Cyclic structure Sequential depth is undefined. 无法置初
23、态：Circuit is not initializable. No tests can be generated for any stuck-at fault. 故障都不可测：After expanding the circuit to 9Nff = 81, or fewer, time-frames ATPG program calls any given target fault untestable. 通过对比多拍结果可以观察到错误：Circuit can only be functionally tested by multiple observations. 故障模拟无法给出故障覆
24、盖率：Functional tests, when simulated, give no fault coverage.,2019/10/21,39,Adding Initializing Hardware,F1,F2,CNT,Z,Initializable modulo-3 counter,CLR,s-a-0,s-a-1,s-a-1,s-a-1,Untestable fault Potentially detectable fault,2019/10/21,40,Benchmark Circuits,Circuit PI PO FF Gates Structure Seq. depth To
25、tal faults Detected faults Potentially detected faults Untestable faults Abandoned faults Fault coverage (%) Fault efficiency (%) Max. sequence length Total test vectors Gentest CPU s (Sparc 2),s1196141418529 Cycle-free4 1242 123903099.8100.0331310,s1238141418508 Cycle-free4 1355 1283072094.7100.033
26、0815,s14888196653 Cyclic - 1486 13842267693.194.824525 19941,s14948196647 Cyclic - 1506 13792309791.693.428559 19183,2019/10/21,41,Test Generations Systems,分类 Target a fault Reverse-time processing Forward-time processing Forward and reverse-time processing Target no specific fault Simulation based
27、algorithms,2019/10/21,42,Reverse-time processing,逆时帧方法 Determine a PO where the fault-effect will appear Backtrace within the time frame to excite and or propagate a fault/fault-effect If not possible go add a timeframe (previous timeframe) and continue,2019/10/21,43,Positives and Negatives,优点 缺点,Lo
28、w memory usages Timeframe added when needed Ability to determine if a fault is untestable,Hard to determine the PO where fault will be detected During backward motion, often the timeframe is assumed to be fault-free, this can generate invalid tests Test application is in the order opposite to test g
29、eneration,2019/10/21,44,Forward-time processing,顺时帧方法 Excite a fault in the present timeframe If excited, propagate to an output, else add a timeframe and then excite continue till fault excited Try to propagate the fault, if not successful, add timeframe and continue the process till fault detected
30、 at a PO,2019/10/21,45,Forward and reverse-time processing,顺时帧与逆时帧结合方法 Perform the fault effect propagation in forward time Perform excitation (justification) in reverse time using fault-free circuit,2019/10/21,46,Positives and Negatives,优点 缺点,Medium memory usages Timeframe added when needed in reve
31、rse as well as in forward time Ability to determine if a fault is untestable,During backward motion, often the timeframe is assumed to be fault-free, this can generate invalid tests Test application is in the order opposite to test generation,2019/10/21,47,FASTEST approach,Use controllability values
32、 to determine the timeframe where the fault can be excited Use observability values to determine the timeframe where the fault will be observed Together these will determine the number of timeframes need to detect the fault of interest Work with that many timeframes in combinational mode to generate
33、 a test sequence in forward time,2019/10/21,48,General comments,Store state information during test generation for later use Preprocess the circuit and learn about implication etc. Reuse previous solutions Modify easy/hard and SCOAP to better suit needs of the sequential ATPGs Make a better selectio
34、n of the target fault as in FASTEST Neither 5-v nor 9-v are complete algorithms for sequential ATPG Multiple timeframe observation a possible solution but has not found way in practice,2019/10/21,49,Simulation based systems,Difficulties with time-frame method: Long initialization sequence Impossible
35、 initialization with three-valued logic Circuit modeling limitations Timing problems tests can cause races/hazards High complexity Inadequacy for asynchronous circuits Advantages of simulation-based methods Advanced fault simulation technology Accurate simulation model exists for verification Variet
36、y of tests functional, heuristic, random Used since early 1960s,2019/10/21,50,Using Fault Simulator,Fault simulator,Vector source: Functional (test-bench), Heuristic (walking 1, etc.), Weighted random, random,Fault list,Test vectors,New faults detected?,Stopping criteria (fault coverage, CPU time li
37、mit, etc.) satisfied?,Stop,Update fault list,Append vectors,Restore circuit state,Generate new trial vectors,Yes,No,Yes,No,Trial vectors,2019/10/21,51,Summary,Combinational ATPG algorithms are extended: Time-frame expansion unrolls time as combinational array Justification via backward time Cycle-fr
38、ee circuits: Require at most dseq+1 time-frames Always initializable Cyclic circuits: May need 9Nff time-frames Circuit must be initializable Partial scan can make circuit cycle-free,2019/10/21,52,Summary (contd.),Sequential test generators classified FASTEST discussed Fault simulation is an effective tool for sequential circuit ATPG. Simulation-based methods produce more vectors, which can potentially be reduced by compaction. A simulation-based method and purely forward time test generators cannot identify untestable faults.,
