1、Carl Culshaw, Systems Engineering, Automotive MCU,ARM Cortex in Automotive Architecture & Peripherals,KFA family, rev A,Oct 24.2014,Agenda,KFA series KFA family architecture Safety Performance Clocking Power Management ADC & triggering subsystem Compatibility Communication peripherals FlexIO Softwar
2、e and Enablement Summary,KFA Series - Introduction,Key Hardware Features High performance ARM Cortex architecture Low power 30% better than todays benchmark Scalability from 16KB to 2MB embedded flash FlexCAN with CAN FD option FlexIO for configurable number of LIN, SPI, I2C Targeting ASIL-B applica
3、tions SecurityKey Software Features KDS (Kinetis Design Studio) Autosar MCAL and OS Non-autosar Low-Level Drivers Model-based design support Extensive 3rd party offering,General Purpose MCU Roadmap,2014,2015,2016,2017,Entry,90nm,First Sample Date (left edge),Product Qualification (right edge),Propos
4、al,Planning,Production or Execution,180nm,Last Updated 10SEP14,2018,KFA 512 M4 up to 120MHz,KEA64 M0+ 40MHz,KEA8 M0+ 48MHz,Mainstream,High performance,KEA128 M0+ 48MHz,64-128kB, LIN, CAN, 64-80pin,16-64kB, LIN, 32-64pin,8kB, LIN, 16-24pin,256-512kB, FlexIO, CAN-FD, 48-144pin,64-128kB, LIN, CAN, 32-6
5、4pin,KFA 1MM4 up to 150MHz,768kB-1M, FlexIO, CAN-FD, 100-176pin,KFA 2M M4/M0+ up to 180MHz,1.5M-2M, FlexIO, CAN-FD, Ethernet, Security 100-176pin,KGA 128 M0+ 64MHz,16-32kB, LIN, 20-48pin,KGA 32 M0+ 48MHz,High temp (AEC Grade 0),Cortex M4/M0+,KFA512 Block Diagram,Preliminary and subject to change,Com
6、munications I/O System,Peripheral Bus,SWD JTAG Debugger,Debug,RAM Up to 64KB,System,Peripheral Bridge,Flash Up To 512K,NVIC,Cortex M4 80/120MHz FPU, DSP, MPU,EEPROM 4KB,2x16ch, 12bit Dual ADC,2 ACMP,Flex IO peripheral,16ch / 64ch eDMA,WDT,EWM,PMC 2.7 - 5.5V,POR,FLL Clk Mult,LVD,Ext Osc (4 - 40MHz),I
7、nt R/C OSC (48MHz 1%),Int LP Osc (128KHz),SCG,High performanceARM Cortex M4 up to 120MHz w FPUeDMA from Qorivva familySoftware Friendly ArchitectureHigh RAM to Flash ratioIndependent CPU and periph clocking48MHz IRC no PLL init required in LPregisters maintained in all modesProgrammable triggers for
8、 ADC no sw delay counters or extra interrupts Functional safety ISO26262 support for ASIL B or higherMPUECC on Flash/Dataflash and RAM Independent internal OSC for WatchdogDiversity between ADC and ACMPDiversity between SPI/SCI and FlexIOCore self test librariesScalable LVD protectionLow powerLow le
9、akage technologyMultiple VLP modes and IRC combosWake-up on analog thresholds,4x8ch 16-Bit FlexTimer,2 I2C,3 SPI,4 SCI (LIN),2 PDB,3 FlexCAN w FD,1 PIT,Open- Drain IO, KBI, GPIO,Digital Components,5V Analogue Components,MCU Core and Memories,1 API,RTC,Operating Characteristics I/OsVoltage range: 2.7
10、 to 5.5 V 64/100pin compatible within FamilyTemperature (ambient): -40 to 125C Open-drain for 3.3V and hi-drive pins to save BOM Powered ESD protection,Safety,Know Your Safety System Context,How to make the system safe?Optimal partitioning between Safety System HW & SW measures scaled to complexity
11、of vehicle safety functionSimple Safety Functions are implemented on a high abstraction level (vehicle & ECU)Complex* Safety Functions are implemented using a combination of low (MCU HW) and high abstraction level (vehicle & ECU),Complex Safety Function (e.g. EPS),Simple Safety Function (e.g. Airbag
12、),EPS, ESP, Engine Management HEV,ASIL D target,ASIL A target,ASIL B target,ASIL C target,* A Complex Safety Function (vehicle level) here refers to the combination of a high computational demand for the application combined with a short control cycle.,Safety System HW & SW,Airbag, Body, DIS,RADAR a
13、nd Vision based ADAS,The Solution,Offering products scaled to vehicle safety function complexity from across the Freescale product portfolioISO 26262 developed products cover the complete rangeStandard products cover systems with simple safety functions Where we enable the customer to do the Qualifi
14、cation, testing and analysis to prove that our component is suitable for the purpose of his safety concept.,Covering the whole range efficiently ,ASIL D target,Complex Safety Function,Simple Safety Function,ASIL A target,ASIL B target,ASIL C target,EPS, ESP, Engine Management HEV,Safety System HW &
15、SW,Airbag, Body, DIS,RADAR and Vision based ADAS,SafeAssure SEooC HW Developed for ISO 26262 (10.9 Safety Element out of Context),SafeAssure Standard HW Enabled for ISO 26262 (8.13 Qualification of Hardware Components),Full ASIL safety tracking KFA family sample extract,Single Point Fault Metric RAM
16、 ECC Flash ECC Undervoltage monitoring Clock Monitoring Temporal protection Software Watch dog SMPU execution control Register protection CRC Individual Peripheral safety support measures,ECC Error Handling Single bits: Flash handled / repaired automatically Single bits: SRAM Error address capturing
17、 Interrupt generated Customer s/w can handle Double bits: Code Flash Machine Exception - software decision If second double bit error - force h/w reset Double bits: Data Flash & SRAM Machine Exception - software decision Customer s/w can handle,Functional Safety,Diversity of safety levels LPSPI or L
18、PSCI v FlexIO Create completely alternate SPI / SCI communication paths Ultra high parallelisation of data integrity Analogue input monitoring Analogue measuring via completely independent system resources Independent references, independent peripherals Class leading monitoring protection schemes,Sa
19、fety Support (Cyclic Redundancy Check - CRC),The cyclic redundancy check (CRC) module generates 16/32-bit CRC code for error detectionThe CRC module provides a programmable polynomial, seed and other parameters required to implement a 16-bit or 32-bit CRC standard.The 16/32-bit code is calculated fo
20、r 32 bits of data at a time.,CRC Engine,CRC Data,Polynomial,Example: Using DMA for CRC Calculation,11,LPUARTs,LPSPIs,I2Cs,FTMs,ADCs,HSCMPs,FlexIO,PDB,GPIOs,63 DMA Requests,SCG,SIM,clock,NVIC,error int,DMA CH0 int,DMA CH1 int,DMA CH16 int,DMA Mux,SPIs,DMA Mux,CRC,Source (Flash),Destination (CRC),Safe
21、ty Support - Watchdog Timer (WDOG),Safety Support - External Watchdog Monitor (EWM),Performance,KFA512 High Level Architecture,Operating profile flash reliability,The below profile is within the targeted development mission profile for qualification and the targeted data retention spec for KFA. Suit
22、able for even the most stringent automotive lighting application. Assume 8000hrs operating (1 year): 2100hrs 125C 3000 105C 1500 40C 1000 25C 400 0CNon-operating (14 years): - 122000hrs 25C average / vehicle stopped,DMA Mux Allocations,Clocking,High Level Clocking Architecture,Clock sources,FIRC: 48
23、MHz 60MHz 1% accuracy after trimming, across PVT 300uA consumption SIRC: 8MHz 10% accuracy 20uA consumption LPO: 128KHz -10% accuracy 2uA consumption XOSC High range: 4MHz 40MHz PLL Choice of FIRC or the XOSC as input sources,Peripheral clock options example of flexibility,Low Power Management,Keep
24、the Energy Budget Low with KFA Intelligent Clock/Speed Selection,This what we call clock scaling & gating Peripheral clocks are disabled by default so there is no wasted power consumption Various clock sources : slow or high speed, internal or external with PLL/FLL to reach higher frequencies OUTDIV
25、 prescaler allow to divide main frequency to supply internal peripherals CG allow to cut clock “manually” per peripherals (in standby or run mode) Automatic platform clocking control in Compute Operation and Partial STOP options further reducing dynamic power consumption Low power boot allow to star
26、t device at slower speed (reducing peak at start),SIM_SCGx registers,Keep the Energy Budget with KFA (contd) Smart Peripherals & Compute mode,Collect Data,Smart Peripherals Transmission and reception of UART signals Generation of PWM signals and/or input capture functionality Triggered Comparator an
27、d or ADC conversions All with the capability of triggering Async DMA request that can transfer data with minimal latency and return to Stop mode,KFA Series,System,FLASH,RAM,DMA 4-ch,Peripheral Bus,Standard peripherals,UART,TIMER,Analog ADC & CMP,Tx/RX,IC/OC,Analog,CORE,Zzz,Compute mode Core, SRAM an
28、d Flash read interfaces remain in Run mode Bus Masters and peripherals are placed in Stop mode,PSTOP 1 =1,2&3 / PSTOP2=1&2 Core / Interrupt Controller Bus Masters (eg: DMA) Bus Slaves (eg: Peripherals) Clock Generation and PMC,Kinetis Extended Power Modes,Run,VLPR,Wait,VLPW,Stop,VLPS,LLS,VLLS3,VLLS2
29、,VLLS1,Recovery Time,_“Typical” Idd Range_,-,-,1.6us,14mA/50Mhz,5us,6us,70us,2.1uA,1.5uA,1.4uA,678nA,867uA 4MHz,509uA 4MHz,310uA,3.5uA,VLLS0,367nA/176nA,7.5mA 50MHz,Kinetis ”K” Cortex M4 across speed grade,Active,Standby mode,Mode,130us,21.5mA/72Mhz,2.6uA,1.9uA,1.59uA,1.47uA,996uA 4MHz,610uA 4MHz,35
30、0uA,5.9uA,NA,12.5mA 50MHz,45mA/100Mhz,4.8uA,3uA,2.2uA,2.1uA,1.12mA 4MHz,770uA 4MHz,590uA,93uA,NA,35mA 100MHz,51mA/120Mhz,250uA,5.6uA,3.2uA,2.8uA,1.4mA 4MHz,926uA 4MHz,1.3mA,250uA,NA,35mA 50MHz,50Mhz,72Mhz,100Mhz,120Mhz,Note : Extract from datasheets product : K20DN128, K20DX128, K20DN512, K20FX512 R
31、un current are at 3V / Code executing from FLASH,KFA512 initial targets, 25C, 105C,Analogue Comparator,Up to 16 analogue inputs available for sampling Fully programmable internal reference voltage Various comparison sources available: Compare against internal fixed reference Compare against internal
32、 variable reference Compare against another pin Supports operation in all power modes Supports cyclic comparison operations when used in conjunction with API / RTC Comparisons stored on per sample basis Configurable to wake up system dependent on compare operation Configurable to drive a pin depende
33、nt on compare operation Note: all registers / timer pulses not shown for simplicity reasons,RTC / API,Free running 32 bit counter 5 different clock sources: FXOSC (8 40MHz) FIRC (48MHz) SIRC (8MHz) LPO (128kHz) Full 32 bit compare functionality Generation of API / RTC interrupts & wakeups Support fo
34、r all power modes Rollover support Use in conjunction with analogue comparator to create fully autonomous low power support Supports cyclic comparison operations when used in conjunction with analogue comparator Configurable to wake up system dependent on compare operation Note: all registers / time
35、r pulses not shown for simplicity reasons,Analogue Comparator / RTC / API interaction,Full STANDBY mode autonomous behaviour Example: Configure the RTC / API to generate a wakeup output every 200ms (from the API_wakeup source) Configure the RTC / API to have a free-running clock output of 1ms period
36、 (RTC.CLK_OUT) Configure the 8 inputs to be read inside the ANL logic (ie unmask all inputs) Software enters the low power STANDBY mode API is free-running After 200ms API asserts a trigger enable to the comparator Read all inputs If different, wake-up else wait for next 200ms time interval,Operatin
37、g Mode overview,Configurable mode availability Configurable mode definition VREG clock sources system clock selection core addresses and clocks peripheral clocks flashes pads Software mode entry Hardware RESET entry Hardware low-power mode exit,Making Effective Use of Power Modes,Scenario: Periodica
38、lly measure 3 analogue inputs every 10ms (eg sensors) Sensors not instantly available for reading Sensor settling time of 2ms Timing and absolute accuracy of initial measurements not critical ADC function active for approximately 9us (3us per conversion) in every 10ms,Proposed solution. Use VLPS - R
39、UN - STOP - RUN - VLPS approach Use API to wake up periodically Clock core and ADC0 from 8MHz SIRC Use STOP state during the sensor stabilization period Return to VLPS unless pre-defined conditions exceeded,2ms,10ms,20mA,35mA,20mA,Run Current range,RUN from RAM,45ms,1ms,10ms,65ms,Run from RAM & read
40、 sensor,45ms,10ms,10ms,Run from RAM & enable sensor,45ms,1ms,10ms,56ms,VLPS Current,300mA,STOP,VLPS,ADC & Triggering Subsystem,KFA512 ADC Configuration,ADC0, ADC1 (12Bit) Channel configuration 16 Standard Internal Channels 3 Special Internal Channels Conversion Time = 1us (incl sample) ENOB = 10.5 b
41、its TUE = +/-6bits 700uA 1us conversion,ADC1 12Bit,16 channels,Bandgap Ana Supply VrefH PMC,ADC0 12Bit,16 channels,Bandgap Ana Supply VrefH,ADC Triggering Scheme Overview,The KFA family supports two types of ADC triggering: ADC software triggerADC hardware trigger Using PDB Using LPIT Using TRGMUX,A
42、DC Conversion using DMA Configuration,Trigger starts ADC conversion ADC conversion complete flag starts the DMA 0 DMA 0 copies the ADC result to buffer and generates a link to DMA1 DMA 1 copies next ADC channel ID from buffer to ADC register When BCR is 0 (DMA done flag), DMA interrupt is generated,
43、ADC Hardware Trigger Method 1: Using PDB,PDB is the suggested ADC triggering module. PDB0 is intended to function with ADC0, so as PDB1-ADC1 and PDB2-ADC2. There are dedicated interconnection between the pair of PDB and ADC.,ADC Hardware Trigger Method 2: Using LPIT,LPIT is another optional ADC trig
44、gering module. Different with PDB, LPIT can be used to trigger any of the three ADCs through TRGMUX. But LPIT only supports 4 independent timer channels, which leads to a limitation of only 4 pre-triggers for ADC. The 4 LPIT channels can be used to flexibly trigger any ADC. For example: 4 ch to trig
45、ger 13 ADCs at same time, each ADC with 4 result registers 4 ch to trigger 2 ADCs independently, each ADC with 2 result registers - . Note: LPIT doesnt support ADC_COCO feedback, it needs software to correctly control the ADC trigger timing setting. Note: Following diagram only shows PDB0-ADC0, its
46、the same with PDB1-ADC1 and PDB2-ADC2.,ADC Hardware Trigger Method 3: Direct trigger,For direct ADC trigger (not using PDB or LPIT), the ADC supports up to 4 ADHWTn.,SW pre-trig,OR,0,0,0,SW pre-trig,ADHWT,ADHWTS0,ADHWTS1,Trigger Multiplexing (TRGMUX),Trigger Multiplexing (TRGMUX continued),FlexTimer
47、 Module,FTM source clock is selectable with prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 from Busclock FTM has a 16-bit counter 2 up to 8 channels (inputs/outputs) The counting can be up or up-down Each channel can be configured for input capture, output compare, or PWM generation Input filter
48、 can be selected for some channels New combined mode to generate a PWM signal (with independent control of both edges of PWM signal) Complementary outputs, include the deadtime insertion Software control of PWM outputs Up to 4 fault inputs for global fault control The polarity of each channel is con
49、figurable The generation of an interrupt per channel input capture/compare, counter overflow, at fault condition Synchronized loading of write buffered FTM registers Write protection for critical registers Backwards compatible with TPM on other Freescale MCUs Dual edge capture for pulse and period width measurement Quadrature decoder with input filters, relative position counting and interrupt on Position count or capture of position count on external event,
