1、铝栅、硅栅器件的版图,铝栅工艺MOSFET的结构Structure,Gate,Source,Drain,N阱硅栅CMOS IC的剖面图,以SiO2为栅介质时，叫MOS器件，这是最常使用的器件形式。历史上也出现过以Al2O3为栅介质的MAS器件和以 Si3N4为栅介质的MNS 器件，以及以SiO2+Si3N4为栅介质的MNOS器件，统称为金属-绝缘栅-半导体器件-MIS 器件。以Al为栅电极时，称铝栅器件。以重掺杂多晶硅(Poly-Si) 为栅电极时，称硅栅器件。它是当前MOS器件的主流器件。,硅栅工艺是利用重掺杂的多晶硅来代替铝做为MOS管的栅电极，使MOS电路特性得到很大改善，它使|VTP|
2、下降1.1V，也容易获得合适的VTN值并能提高开关速度和集成度。硅栅工艺具有自对准作用，这是由于硅具有耐高温的性质。栅电极，更确切的说是在栅电极下面的介质层，是限定源、漏扩散区边界的扩散掩膜，使栅区与源、漏交迭的密勒电容大大减小，也使其它寄生电容减小，使器件的频率特性得到提高。另外，在源、漏扩散之前进行栅氧化，也意味着可得到浅结。,铝栅工艺为了保证栅金属与漏极铝引线之间有一定的间隔，要求漏扩散区面积要大些。而在硅栅工艺中覆盖源漏极的铝引线可重迭到栅区，这是因为有一绝缘层将栅区与源漏极引线隔开，从而可使结面积减少30%40%。硅栅工艺还可提高集成度，这不仅是因为扩散自对准作用可使单元面积大为缩小
3、，而且因为硅栅工艺可以使用“二层半布线”即一层铝布线，一层重掺杂多晶硅布线，一层重掺杂的扩散层布线。由于在制作扩散层时，多晶硅要起掩膜作用，所以扩散层不能与多晶硅层交叉，故称为两层半布线铝栅工艺只有两层布线：一层铝布线，一层扩散层布线。硅栅工艺由于有两层半布线，既可使芯片面积比铝栅缩小50%又可增加布线灵活性。,简化N阱硅栅CMOS工艺演示,氧化层生长,曝光,氧化层的刻蚀,光刻1，刻N阱掩膜版,N阱注入,光刻1，刻N阱掩膜版,形成N阱,氮化硅的刻蚀,N阱,P-SUB,场氧的生长,N阱,P-SUB,去除氮化硅,N阱,P-SUB,重新生长二氧化硅（栅氧）,N阱,P-SUB,生长多晶硅,N阱,P-S
4、UB,刻蚀多晶硅,N阱,P-SUB,刻蚀多晶硅,N阱,P-SUB,场氧化层,栅氧化层,P+离子注入,N阱,P-SUB,N+离子注入,N阱,P-SUB,生长磷硅玻璃PSG,N阱,P-SUB,光刻接触孔,N阱,P-SUB,刻铝,N阱,P-SUB,刻铝,N阱,P-SUB,N阱,P-SUB,铝栅PMOSFET的制造流程,Step 0: Start with a bare n-type silicon wafer.,N Doped Silicon,*Step 1: (layering) Grow thick layer (5000) of silicon dioxide (field oxide) to
5、 act as a doping barrier.,*Step 2a: (patterning) Apply photoresist.,Source/Drain: Photomask (dark field) mask 1,Clear Glass,Chromium,Cross Section,Step 2b: (patterning) Expose photoresist to create temporary pattern for source/drain regions.,N Doped Silicon,Thick Field Oxide,Photoresist,Ultraviolet
6、Light,Photomask,Step 2c: (patterning) Develop photoresist, completing temporary pattern for source/drain regions.,N Doped Silicon,Thick Field Oxide,Photoresist,Step 2d: (patterning) Wet etch permanent openings for source/drain into field oxide.,N Doped Silicon,Thick Field Oxide,Photoresist,Step 2e:
7、(patterning) Remove photoresist. Permanent pattern remains in the silicon dioxide.,N Doped Silicon,Thick Field Oxide,Source/Drain Windows: Microscope View mask 1,Bare Silicon,Thick Field Oxide,Cross Section,*Step 3a: (doping) Apply p-type spin-on dopant film. Boron penetrates into the silicon throug
8、h the holes in the field oxide to begin formation of the source and drain regions.,N Doped Silicon,P+ Drain,P+ Source,Thick Field Oxide,Boron-Doped Spin-On Oxide,Step 3b: (heat treatment) Drive dopants deeper into silicon using high temperatures (1000), completing formation of the source and drain r
9、egions.,N Doped Silicon,P+ Drain,P+ Source,Thick Field Oxide,Boron-Doped Spin-On Oxide,P+ Drain,P+ Source,Channel Length - Leff,Step 4a: (layering) Wet etch to remove SOD (spin-on dopant) and field oxide layers.,N Doped Silicon,P+ Drain,P+ Source,Source/Drain Doping: Microscope View Mask1,P+ Doped S
10、ource and Drain (not actually visible),N-Doped Substrate,Cross Section,*Step 4b: (layering) Regrow new field oxide layer.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Oxide grows slightly thicker over doped areas.,*Step 5a: (patterning) Apply photoresist.,Thick Field Oxide,N Doped Silicon,P+
11、 Drain,P+ Source,Photoresist,Gate: Photomask (dark field) mask2,Clear Glass,Chromium,Cross Section,Step 5b: (patterning) Expose photoresist to create temporary pattern for gate region.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Photoresist,Ultraviolet Light,Photomask,Step 5c: (patterning)
12、Develop photoresist, completing temporary pattern for gate region.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Photoresist,Step 5d: (patterning) Wet etch permanent opening for gate region into field oxide.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Photoresist,Step 5e: (patterning
13、) Remove photoresist. Permanent pattern remains in the silicon dioxide.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,*Step 6: (layering) Grow thin layer (700) of silicon dioxide to act as the gate oxide for the transistor.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,
14、After Gate Oxide Growth: Microscope View,P+ Doped Source and Drain (under Field Oxide),Thick Field Oxide,Thin Gate Oxide,Cross Section,*Step 7a: (patterning) Apply photoresist.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Photoresist,Step 7b: (patterning) Expose photoresist t
15、o create temporary pattern for contact holes.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Photoresist,Ultraviolet Light,Photomask,Contacts: Photomask (dark field) mask 3,Clear Glass,Chromium,Cross Section,Step 7c: (patterning) Develop photoresist, completing temporary patter
16、n for contact holes.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Photoresist,Step 7d: (patterning) Etch permanent holes for contacts into field oxide.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Photoresist,Step 7e: (patterning) Remove photoresist. P
17、ermanent contact holes in the field oxide remain.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,After Contact Patterning: Microscope View,Contact Hole (bare silicon),P+ Doped Source and Drain (under Field Oxide),Thick Field Oxide,Thin Gate Oxide,Cross Section,*Step 8a: (layeri
18、ng) Deposit aluminum layer over entire wafer surface.,Metal,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Step 8b: (heat treatment) Alloy aluminum at moderate temperatures (450) to form good electrical contact with silicon.,Metal,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ S
19、ource,Thin Gate Oxide,Alloyed Aluminum-Silicon,*Step 9a: (patterning) Apply photoresist.,Metal,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Photoresist,Step 9b: (patterning) Expose resist to create temporary pattern to define metal interconnects and gate electrode.,Metal,Thic
20、k Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Photoresist,Ultraviolet Light,Photomask,Metal Interconnects: Photomask (light field),Chromium,Clear Glass,Cross Section,Step 9c: (patterning) Develop photoresist, completing temporary pattern for metal interconnects and gate electrode.
21、,Metal,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Photoresist,Step 9d: (patterning) Etch permanent pattern into metal for interconnects and gate electrode.,Step 9e: (patterning) Remove photoresist. The PMOS Transistor is now complete! Step 10: Test devices for functionality and performance. Step 11: Go out for a beer!,Completed Product: Microscope View,Source Bond Pad,Drain Bond Pad,Gate Bond Pad,Aluminum,Thin Gate Oxide (under metal),Contact Hole (under metal),P+ Doped Source and Drain (under field oxide and metal),Thick Field Oxide,Cross Section,
