1、Version Change part DescriptionV0.1 First version releaseV0.11MT6582_BBDelete DRAM part typo(For LPDDR2，MT6582E9(RCLK0)與F9(RCLK0_B)请悬空)MT6582_BBModify description ofHW pin必须注意外部使用的DRAM电压. (VM fromMT6323)DRAM为LP-DDR2時, MT6323 pin B7(SPI_CSN),MT6323 pin E7(AUD_MOSI) 不可以有外部上下拉元件.即保持SPI_CSN=PU, AUD_MOSI
2、=PD即可. Thermal New releaseMT6323_PMIC Change ballname diagramV0.12MT6582_BBDelete DRAM part typo :(For LPDDR2，MT6582E9(RCLK0)與F9(RCLK0_B)请悬空)MT6323_PMICDelete typo :AUXADC_VREF18 靠近PMIC side 需加 0.1uF 電容 to AVSS28_AUXADCESD Delete RTP partMT6323_PMIC Modify VCN_3V3 trace wide suggestion.VCN_3V3: trac
3、e wide (20mil)MT6627_ConnectivityModify VCN33 routing width suggestionVCN33 routing width = 20mil, and place = 2vias for layer transition.MIPI CSI Modify typo :The placement of MIPI VRT 1.5K 1% precisionresistor must close to BB chip and MIPI_VRTtrace needs well ground shielding.V1.0 MT6323_PMICUSB
4、DL w/o bat :Please connect 1k resistor from key toFCHR_ENB pin and place close to FCHR_ENBpin.Date2013.03.292013.04.262013.04.262013.04.262013.04.262013.05.282013.05.282013.05.282013.05.282013.05.282013.05.282013.07.15Type Function ComplianceCommonLayout Clock Layout PWM Layout power Project dep.Sch
5、ematicHW pin HW pin HW pin HW pin JTAG HW i2C ABBpower AUXADC GPIOpower Layout ABBpower Item32K/26M等时钟信号建议包地，避免跟其他信号相邻而造成干扰PWM信号建议包地，避免跟其他信号相邻而造成干扰对于可能流大电流的走线，如VBAT/VBUS/各个buck和LDO的路径，充电电路，背光电流输出路径，闪光灯电流路径等，最好上下左右包地，其次要避开敏感信号走线（如高速信号，模拟信号，I2C等）必须注意外部使用的DRAM电压. (VM from MT6323)DRAM为LP-DDR2時, MT6323 p
6、in B7(SPI_CSN), MT6323 pin E7(AUD_MOSI) 不可以有外部上下拉元件.即保持SPI_CSN=PU, AUD_MOSI=PD即可. Pin: TESTMODE, 必须接GND.Pin: FSOURCE, DVDD18_EFUSE 接GNDKCOL 0 外部绝对不可以有external pull down resistorMT6582 JTAG為pin AF12(JTCK), AE12(JTDO), AG11(JTDI), AF13(JTMS) 與MT6323 pin M25(SYSRSTB)使用专用i2C 出口時, 必須加上拉電阻(建議4.7K)MT6582 A
7、nalog BB power 加上必要的稳压电容MT6582不支持RTP, 故pin AF18, AG17, AF17, AG16 無用途务必遵守MT6582 High voltage IO Overview 以提供IO正确电源专用GND球必须先接回电容(不可直接先接主地), 再接GND)Requirement Risk impactMust IO reliabilityMust IO reliabilityMust IO reliabilityMust system bootingMust system bootingMust system bootingMust system bootin
8、gMust debug requirement (JTAG pin out)Must Camera/ATV/MEMS sensors operationMust system stability, MIPI/USB/RF perfromanceConditionalMust system stability and IO reliabilityMust system stability, MIPI/USB/RF perfromanceValidation NoteNANANANANANANANANANANANANAType Function ComplianceSCHSPEECH ACCDET
9、LayoutSpeechACCDET Project dep.Schematic Speech ACCDET Layout Speech ACCDET TYPE Function ComplianceCommonSCHAudioPCBProject dep.SCHAudioPCB Common AudioPCBItem2 mic bias- MICBIAS0 为主板上mic供电，在靠近PMIC输出端默认加 100nF cap. 如果使用数字mic，需要使用1uF；- MICBIAS1 为耳机mic供电，不要直接添加任何电容在MICBIAS1输出端。Add 470 ohm Pull Low Re
10、sistors at HPL / HPR耳机中断switch PIN上拉470K 欧姆电阻，请注意 power domain必须与HP_EINT相同耳机中断switch PIN到HP_EINT之间串联47K电阻，需要在上拉点之后ACCDET到HP_MIC之间添加1K电阻目前推荐的耳机检测方式是EINT+ACCDET，请使用带中断的耳机接口(default open type)，MIC输入走线，receiver输出走线需要平行差分走线，并且上下左右包地处理，小板和FPC走线也需要注意。MIC 摆放位置应远离RF PA及VBAT trace , 避免零件震动音透过MIC 传递MICBIAS0/1需
11、要全方位包地，并且远离高频信号和大电流。MIC和听筒的滤波器件，TVS的GND要连接一起后通过via连接到主地，不能直接连接表层GND，容易耦合RF noise；如果使用外部PA，请将PA参考GND走线与HPL/R一起差分走线到MT6323附近再下地。ACCDET Layout需要上下左右包地，远离高频信号走线和大电流走线。或將ACCDET 上1K電阻靠近PMU IC減少走線的距離ItemFor Class-AB SPK Amp建议预留一组Bead滤波，靠近喇叭 ；可以先用0 ohm替代 , 若无EMS相关问题 ,可以移除For Class-D SPK Amp 建议预留一组Bead滤波，靠近I
12、C ；可以先用0 ohm替代 , 若无EMI相关问题,可以移除HPR 和 HPL (Audio buffer) 对地器件Cload总和不能超过250pF，包括电容，以及滤波器件的等效电容。AU_HSP和 AU_HSN之间（Voice buffer）的器件等效电容需要小于 250pF，SPKP0 到 SPKN0 之间（Internal Audio PA）的器件Cload总和不能超过 330p，VA_PMU需要先经过电容之后再输入给AVDD28_ABB和AVDD28_AUXADC；且电容GND需要先与GND_ABB连接之后再单点下到主地。电容尽量靠近PMIC。VBAT_SPK 输入电容尽量靠近PI
13、N脚，GND_SPK需与输入电容GND连接之后再连接到主GND。左右声道需要分别上下左右包地，L/R之间一定要用GND隔开；VBAT_SPK宽度尽量宽 , 距离短。建议不要小于25mils （For internal PA use recommend）SPK Amp 的走线，宽度尽量宽 , 距离短，并且做好包地处理。For Class D（默认），需要用GND隔开；For Class AB ，需要并排差分走线。从SPKP and SPKN 到喇叭的长宽比建议小于100（L/W 600mA Drop output swing,output max powerreduceSerial Bead p
14、laced at SPKAMP output,and select power line spec forlarge current requirement.Vdrop = I * RIf RDC=0.5ohm Rated currnet=500mAoutput swing drop 250mVmust HW limitation 所有Trace 上component 的等效容值均須列入計算must HW limitation 所有Trace 上component 的等效容值均須列入計算must HW limitationmustmustmustConditionalDrop output s
15、wing,output max powerreduceConditionalmust电容值可选，容值越大，性能越好。具体可参考Audio_AC_couple_cap_performance enhancement.ppt所有Trace 上component 的等效容值均須列入計算所有Trace 上component 的等效容值均須列入計算Type Function Compliance使用說明ProjectdependentSCHMemory(LPDDR2)PlacementPCBSignal Integrity:Power Integrity:ProjectdependentMemory(L
16、PDDR2)ProjectdependentMemory(LPDDR2)PCBItemThe simplified check list is a notice of basic dram layout design. Please refer to MMD or reference phone memory layout. If one of these items cant meet the rule,system crash might happen. BB DVDD12_EMI(Vm) capacitor:For the five bypass capacitors(0.1uFx4,X
17、5R ; 4.7uFx1) in the reference schematic, their placement must be close to DVDD12_EMI pins ofBB chip.MCP DVDD12_EMI(Vm) capacitor:For the four bypass capacitors(2.2uFx2,X5R) in the reference schematic, their placement must be close to DVDD12_EMI pins of MCP.The four bypass capacitors(0.1uFx4,X5R) mu
18、st be close to BB power pin, 1st priority is to put them to the bottom layer, dont put themthe space between MCP& BB due to Signal Integrity concern.Check if MCP is as close to BB IC as possible:The distance(gap) from BB package to MCP package 10mils, and avoid the Power/GNDpassageway to be broken.C
19、apacitor Power & GND via hole:The ratio of capacitors pad, small via, PTH via= 1:2:1 is recommended, and via must be close to pad, PTH via must connect intopower/GND plane.Signal Integrity:Power Integrity:DVDD12_EMI Trace from PMIC to DVDD12_EMI plane:The number of trace via due to layer change is m
20、ore than 2pcs PTH via or 4pcs small via, and put one capacitor near the joint of theplane and trace. The trace width 25mil.Requirement Risk impactYes(1)PMU output need total 10uF capacitor(2)LPDDR2 PDN simulationYes(1)PMU output need total 10uF capacitor&voltage drop concern(Q=I*t=CV)roughly evaluat
21、ed:600mA*2us*0.5=C*60mV = C=10uF(2)4.7uF on PMU output sideYes PDN simulation concernYes data rate: 1066 SI concernYes PDN simulation concernYes data rate: 1066 SI concernYes data rate: 1066 SI simulation concernYes data rate: 1066 SI simulation concernYes data rate: 1066 SI simulation concernYes PD
22、N simulation concernYes PDN simulation concernYes PDN simulation concernNeed to simulation or Re-test itemVm voltage drop measurement:(1)measurement point: BB cap. group(2)Vm noise need to meet JEDEC spec.: 1.14V1.3V(3)test scenario: 3D Nenamark2 loop(contact MVG to know the details)Vm voltage drop
23、measurement:(1)measurement point: the closest MCP cap. (2)Vm noise need to meet JEDEC spec.: 1.14V1.3V(3)test scenario: 3D Nenamark2 loop(contact MVG to know the details)(1)3 grid(HTLV/LTHV/NTNV) ETT(2)3 grid stress test(3D Nenamark2 loop)Note:HT:65, LT=-20LV: Vcore=0.945V, Vm=1.14VHV: Vcore=1.155V,
24、 Vm=1.30Vprovide layout file to MTK for checking(1)3 grid(HTLV/LTHV/NTNV) ETT(2)3 grid stress test(3D Nenamark2 loop)Note:HT:65, LT=-20LV: Vcore=0.945V, Vm=1.14VHV: Vcore=1.155V, Vm=1.30Vprovide layout file to MTK(1)3 grid(HTLV/LTHV/NTNV) ETT(2)3 grid stress test(3D Nenamark2 loop)Note:HT:65, LT=-20
25、LV: Vcore=0.945V, Vm=1.14VHV: Vcore=1.155V, Vm=1.30Vsame as abovesame as abovesame as abovesame as abovesame as aboveType Function Compliance使用說明Project dep.SchematicCore &CPUPlacement LayoutPower Integrity:Item以下简易check list为dram基本设计之提醒事项, 请参照MMD或ref. phone走线方式,若有一项无法follow, 可能发生严重无法开机或当机情形VPROC/VC
26、ore capacitor:Reference design所放的bypass电容为6颗0.1uF(Bottom cap区 of 1st cap group)、 4颗1uF(Bottom cap区 of 1st cap group) 和 5颗10uF电容(1st cap group), layout位置必须靠近BB chip VCCK_VPROC/VCCK pins。(1) 若为双面上件: 在Bottom cap区放上6颗0.1uF、 4颗1uF ，放置位置离VCCK_VPROC/VCCK balls愈近愈好。其余bypass 电容放在1st groupcap区。(2) 若为单面上件: 请将6
27、颗0.1uF、 4颗1uF放在1st group cap区(与BB & 5颗10uF电容放在同一面)。(1) 单双面上件之1st group cap至VCCK_VPROC/VCCK的wide power trace。PWR总共采用2 层走线，L1线长 350mil；L1线宽 110mil(2) 双面上件，请将bottom cap以Via直接串接电容和wide power trace ，使距离(L2)愈短愈好。 Bottom cap至 5颗10uF电容之PWR trace采用一层走线，L1线长 500mil；L1线宽 100mil，总共使用1 层PWR/1层GND平行走线Capacitor Po
28、wer & GND via打法:.大小孔比例原则- pad: Laser via : PTH via=1:2:1, 且不论盲埋孔必须靠近pad, 大孔必须直接下到power/GND planeVCCK_VPROC & GND plane:(1) VCCK_VPROC via数量的最低需求是：18小孔(盲孔)配13大孔(埋/PTH孔)。(2) Ground via尽量靠近power via。第一电容群拉出一对反馈(VPROC_FB/GND_VPROC_FB)网络回到MT6323(PMIC)，此对走线为一电压侦测电路，必须减少其他讯号对它的耦合效应。 因此，请在走线或换层via孔都做ground shielding的保护。Power Integrity:RequirementYesYesYesYesYesYesRisk impactValidation Note
