1、ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 7/46 2007-3-22 1 .Introduction ATJ2063 is a third generation single-chip highly-integrated digital music system solution for devices such as dedicated audio players, PDAs, and cell phones. It inclu
2、des an audio decoder with a high performance DSP with embedded RAM and ROM, USB interface for downloading music and uploading voice recordings. ATJ2063 also provides an interface flash memory, LED/LCD, button and switch inputs, headphones. ATJ2063 contains a high performance DSP, which can easily be
3、 programmed to support many kinds of digital audio standards such as WMA, etc. For devices like USB-Disk, ATJ2063 can act as a USB mass storage slave device to personal computer system. ATJ2063 has low power consumption to allow long battery life and an efficient flexible on-chip DC-DC converter tha
4、t allows many different battery configurations, including 1xAA and 1xAAA. The built-in Sigma-Delta DAC includes a headphone driver to directly drive low impedance headphones. ATJ2063 provides a true “ALL-IN-ONE” solution that is ideally suited for highly optimized digital audio players. Features: MP
5、EG1/2/2.5 Audio Layer 1,2,3 decoder, bit rate 8-448Kbps, 8-48KHz, CBR/VBR Support WMA Decoder, bit rate 32-384Kbps, 8-48KHz 24 bits DSP Core with on-chip Debug Support Unit (DSU) On-chip DSP PM with SRAM(16K*24) ,can be switched to be MCU memory space On-chip DSP DM with SRAM(16K*24), can be switche
6、d to be MCU memory space Integrated MCU with DSU, the instruction set is compatible with Z80 ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 8/46 2007-3-22 Internal (16K-64)x8(ZRAM1),(3K+3K)(ZRAM2) and 6k ZRAM3 accessed by MCU Internal 12Kx8 BRO
7、M build in Boot up and USB Upgrade firmware Internal (21K+17K)x8 TROM Internal SRAM access time92dB,without A weight=88dB A/D SNR 79dB Headphone driver output 2x11Mw 16ohm Operating Voltage: IO: 3.0v, Core: 1.8v Standby Leakage Current: VCC:50uA3.0V(MAX), VDD: 350uA1.6V(MAX) Low Power Consumption :
8、80mW1.5V at typical WMA decoder solution ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 10/46 2007-3-22 2.2 Pin Definition NOTE: 1 ： PWR-Power Supply 2 ： AI-Analog Input 3 ： AO-Analog Output 4 ： O-Output 5 ： I-Input 6 ： BI-Bidirection 7 ： TBD2C
9、, BD2C, BD2XU, SBD2X, BD2XM5-2 miliampere driver 8 ： BD4CM2, BD4C, BD4CU-4 miliampere driver 9: BD1XM2-1 miliampere driver 10：USCU-USCHIMITCU Pin No. Pin Name I/O Type Driver Reset DefaultDescription 1 VCC PWR / / Power supply for USB 2 UREG AO / / USB precision Resistor 3 GND PWR / / USB ground 4 U
10、SBDP A / H USB data plus 5 USBDM A / H USB data minus 6 RESET- I USCU H System reset input (active low) 7 PAVCC PWR / / Power supply for power amplifier 8 AOUTR AO / / Int. PA right channel analog output 9 AOUTL AO / / Int. PA left channel analog output 10 PAGND PWR / / Power amplifier ground 11 VRD
11、A AO / / Bypass capacitor connect pin for Int. D/A Reference voltage 12 NC / / / / 13 NC / / / / 14 NC / / / / 15 NC / / / / ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 11/46 2007-3-22 16 AGND PWR / / Analog ground 17 AVCC PWR / / power supp
12、ly of Analog 18 VREFI AI / / Voltage reference input 19 AVDD PWR / / Analog Core power pin 20 VDDIO PWR / Z Core power input/output 21 VP PWR / / Power pin 22 LRADC1 AI / / Low resolution A/D input 1 23 PWRMode0 AI / / POWER mode select 0 24 HOSCI AI / / High frequency crystal OSC input 25 HOSCO AO
13、/ / High frequency crystal OSC output 26 VCC PWR / / PAD power pin 27 BAT I / / Battery Voltage input. GPIO_B0 BI Z Bit0 of General purpose I/O port B 28 KEYI0 I BD2C H Bit0 of key scan circuit input 29 GPIO_C2 BI BD4CM2 / Bit2 of General purpose I/O port C GPIO_B2 BI Z Bit2 of General purpose I/O p
14、ort B KEYI12 I H Bit1 of key scan circuit input 30 SPI_SCK O BD2XU M5 / SCK of SPI 31 LXVDD PWR / / VDD DC-DC pin 32 GND PWR / / Ground 33 GND PWR / / NMOS Ground 34 LXVCC PWR / / VCC DC-DC pin 35 CE2- O NF_PAD H Ext. memory chip enable 2 36 CE1- O NF_PAD H Ext. memory chip enable 1 CE3- O H Ext. me
15、mory chip enable 3 37 GPO_A3 O BD4CU / Bit3 of General purpose Output port A GPIO_G0 BI Z Bit0 of General purpose I/O port G 38 CE4- O TBD2C / Ext. memory chip enable 4 39 VDD PWR / / Digital Core power ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver
16、. 1.1 12/46 2007-3-22 40 RB- I BD4C H Nand Type flash Ready/Busy status input. GPO_A1 O L Bit1 of General purpose Output port A 41 ICECK I BD4C / Clock input of DSU GPO_A2 O L Bit2 of General purpose Output port A 42 ICEDO O BD4C / Data output of DSU GPO_A0 O 0 Bit0 of General purpose Output port A
17、43 ICEDI I BD4CM2 / Data input of DSU 44 ICEEN- I BD4C / DSU enable (active low) 45 ICERST- I BD4C / DSU reset (active low) GPIO_B4 BI Z Bit4 of General purpose I/O port B 46 KEYO0 O BD2XM5 / Bit0 of key scan circuit output GPIO_B5 BI Z Bit5 of General purpose I/O port B KEYO1 O / Bit1 of key scan c
18、ircuit output 47 SPI_MOSI O BD2XM5 / MOSI of SPI 48 VCC PWR / / Digital power pad 49 D7 BI NF_PAD L Bit7 of ext. memory data bus 50 D6 BI NF_PAD L Bit6 of ext. memory data bus 51 D5 BI NF_PAD L Bit5 of ext. memory data bus 52 D4 BI NF_PAD L Bit4 of ext. memory data bus 53 D3 BI NF_PAD L Bit3 of ext.
19、 memory data bus 54 D2 BI NF_PAD L Bit2 of ext. memory data bus 55 GND PWR / / Ground 56 D1 BI NF_PAD L Bit1 of ext. memory data bus 57 D0 BI NF_PAD L Bit0 of ext. memory data bus 58 MWR- O NF_PAD H Ext. memory write strobe 59 MRD- O NF_PAD H Ext. memory read strobe 60 CLE O NF_PAD L Command latch e
20、nable for NAND flash 61 ALE O NF_PAD L Address latch enable for NAND flash ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 13/46 2007-3-22 62 GPIO_C1 BI SBD2X OD Bit1 of General purpose I/O port C 63 RB2- I BD4C H Nand Type flash Ready/Busy stat
21、us input 2 64 VDD PWR / / Digital Core power ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 15/46 2007-3-22 3.2 MCU Core 3.2.1 MCU System Memory Mapping 16KB 16KB 32KB IPMM 16KB IPML 16KB IDMH 16KB IDMM 16KB IDML 16KB IPMH 16KB BANK0(32KB) BANK
22、1(32KB) BANK2(32KB) BANK3(32KB)BANK(32KB) Entended Memory Space (MCU.A15=1) Internal Memory Space (MCU.A15=0) MCU 64KB Memory Space 0000H 8000H FFFFH ZRAM2 (3+3) KB ZRAM3 (3+3) KBIf IA15=0 - mapped to internal Memory If IA14=0, mapped to internal ZRAM（16K-64 ZRAM1） If IA14=1, mapped to internal DSP
23、IPM/IDM when they are mapped into MCU memory space 3 extended address bits of a IO mapped register (Mapped at registered are used to decode the access to one of these memory blocks Bit 2 1 0 Accessed Block 0 0 0 IPM low byte ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. Al
24、l rights reserved. Ver. 1.1 16/46 2007-3-22 0 0 1 IPM middle byte 0 1 0 IPM high byte 0 1 1 ZRAM3 1 0 0 IDM low byte 1 0 1 IDM middle byte 1 1 0 IDM high byte 1 1 1 ZRAM2 （B1+B2） Since IPM/IDM is mapped to MCU memory space per 8K block, IA13 is used to select low/high block of 8K bytes in each 16K b
25、yte block. If IA15=1 - Extended address bits are IO mapped at 01h and 02h for EMA15-28. EMA15-25 are output as address bus, while the EMA26-28 are used to decode CE0- CE3-. CE0- is used to access boot code from ROM/MASK/NOR- type Flash. CE1- to CE3- can be configured to access ROM, or RAM or NAND-ty
26、pe Flash. ATJ2063s internal MCU MROM/SRAM memory mapping: 1) (16K-64) byte ZRAM1(IA15=0,IA14=0): 0000H-3FBFH 2) 6Kbyte ZRAM2 (IA15=0, IA14=1, IOReg05.2:0=111): 4000H-57FFH 3) (2K+256) byte URAM: 5800H-60FFH it has synchronization and asynchronism accessing mode. 4) 12Kbyte BROM (IA15=1,Reg02=00h, Re
27、g01=00h): 8000h-AFFFh 5) 21Kbyte TROM1 (IA15=1,Reg02=00h,Reg01=02h): 8000h-D3FFh 6) 17Kbyte TROM2 (IA15=1,Reg02=00h,Reg01=03h): 8000h-C400h 7) 6Kbyte ZRAM3 (IA15=0,IA14=1,IOReg05.2:0=011): 4000H-57FFH ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver.
28、1.1 17/46 2007-3-22 ATJ2063s internal DSP IPM/IDM memory mapping: 1) 16K x24bit IPM SRAM: 0000H-3FFFH 2) 16K x24bit IDM SRAM : 0000H-3FFFH ATJ2063s internal DSP IPM/IDM memory mapping accessed by MCU: 1) 16K x3 byte IPM SRAM: 4000H-7FFFH 2) 16K x3 byte IDM SRAM : 4000H-7FFFH (Hi/Mid/Low Byte Select
29、and Mapping Mode controlled by IOReg05) DMA Mode Notes: 1: When DMA1 and DMA2 are active, MCU will halt, and DMA1 and DMA2 have priority. 2: FLASHDMA or USB DMA is active, MCU will not halt. 3.3 DSP24 Core This Core is a high performance, programmable Digital Signal Processor (DSP) suitable for a va
30、riety of digital audio compounding functions, such as Dolby AC-3 Surround, MPEG1 Layer3 which require large memory provided and the higher accuracy. RDSP24 is a general purpose DSP which can be appended various peripherals circuitry to implement some advanced signal processing algorithms for audio a
31、pplication. 3.4 ZRAM1 and ZRAM2 Input: A13:0, ID7:0, ZRAMRD-, ZRAMWR- Output: RD7:0 (Tri-state) Speed: max read time 30 ns from ZRAMRD- going low ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 18/46 2007-3-22 Power consumption: stand by when bo
32、th WR- and RD- are inactive, access current as low as possible. ZRAM2 is composed of B1 and B2, and each of them is 2k*8 byte SRAM. B1, B2 and ZRAM1(B0) can be operated independently. It has the following modes: 1) MCU running at B0, while DMAM read B1 and DMAN write B2.B1 and B2 are vise versa. M=1
33、, 2, 3, 4, 5, 6; N=1, 2, 3, 4, 5, 6; M!=N. 2) MCU running at B0+B1+B2 or B0+B1 or B0+B2. IPM and IDM Notes: Power consumption: stand by when both WR- and RD- are inactive, access current is as low as possible. PM/DM can be visited by MCU, DSP, DMA1, DMA2 and DMA5. When DSP visits low(high) bytes of
34、8Kbytes, MCU/DMA1,2,5 can visit high(low) bytes of 8Kbytes at the same time. 3.5 USB2.0 SIE 3.5.1 General Description The Actions USB2.0 device controller is fully compliant with the Universal Serial Bus 2.0 specification. In high-speed mode this device is capable of transmitting or receiving data u
35、p to 480Mbps.This high performance USB2.0 device controller integrates USB transceiver, SIE, and provides multifarious interfaces for generic MCU, RAM, ROM and DMA controller. So it is suitable for a variety of peripherals, such as: scanners, printers, mass storage devices, and digital cameras. It i
36、s designed to be a cost-effective USB total solution. ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 19/46 2007-3-22 3.5.2 Features Fully compliant with USB Specification 2.0 Supports USB High Speed (480Mb/s) and Full Speed (12Mb/s) Supports Co
37、ntrol, Bulk, Isoc hronous and Interrupt Transfers Embedded USB high-speed Transceiver which complies with Inter UTMI Supports DMA interface (16-bit) 2K bytes configurable FIFO for endpoints and provides double buffer to increase throughput. Supports USB remote wake-up feature Software controlled con
38、nection to USB bus for re-enumeration ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 20/46 2007-3-22 3.5.3 USB Using Memory 3.6 NAND Flash Interface ATJ2063 can support NAND type flash from 32M to 4G bytes. 3.7 Key Scan Interface KEY Scan Timin
39、g： ZRAM 16K EM 32K IDML 16K IDMM 16K IDMH 16K IPML 16K IPMM 16K IPMH 16K 0000h 4000h 6000h 8000h FFFFh 6100h USB FIFO 2K USB FIFO 192 + 64byte =256byte B1+B2 (ZRAM2) 6K 5800h ZRAM3 6K ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 21/46 2007-3-
40、22 KeyOut0 KeyOut1 KeyOut7 T8 TCycle 1Cycle 2 T=De-bouncing Time/8 Key Scan TimingWhen key scan circuit is enabled, ATJ2063 will scan the keyboard periodically. It drives pin KEYOUTn n=27 scan pulse in turn. When any key is pressed, the corresponding Keyout N will send out the scan pulse. When a key
41、 is pressed, pin Keyin N connecting the key will be found low level. There are 12 internal 8-bit registers for key value latch per scan. But only another one register (Key Scan Data Register) for MCU may access key value. Those 12 internal registers are mapped into this register, and an internal poi
42、nter is used to point to the current register to return scan data when read. Any IO write to this register will clear the internal register, and the pointer will increase by 1 and point to the next register after read is performed. 3.8 LCD Interface It is an ICON LCD control interface. We can operat
43、e 4*19 icons using the 10 registers ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 22/46 2007-3-22 from 0xc2 to 0xcb. ICON LCD 4*19 COM0 COM1 COM2 COM3 SEGn V3 V2 V1 V0 ON=V0 OFF=V2 ON=V3 OFF=V1 n COM0 COM1 COM2 COM3 ON OFF 3 2 +1+1+1 1+1+1+1 1
44、2 2 3 1.732 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 23/46 2007-3-22 3.9 General Purpose IO Ports ATJ2063 has GPOA, GPIOB, GPIOC and GPIOG. They have different functions in different modes. G
45、PIO F1(CE0S=H default) F2(key8*12) F3(ILCD) F4(CE0S=L default)MROM) GPO_A0 GPO_A0/ICEDI GPO_A1 GPO_A1/ICECK GPO_A2 GPO_A2/ICEDO GPO_A3 CE3-/GPOA3/MMC_CMD CE3-/GPOA3 GPIO_B0 KEYI0/GPIO_B0 GPIO_B2 KEYI2/GPIO_B2 KEYI2/GPIO_B2/SPI_SCK GPIO_B4 KEYO0/GPIO_B4 GPIO_B5 KEYO1/GPIO_B5 KEYO1/GPIO_B5/SPI_MOSI GP
46、IO_C1 GPIO_C1 GPIO_C1/I2C_SDA/SIRQ- GPIO_C2 GPIO_C2 /MMC_SCLK GPIO_C2 GPIO_C2 GPIO_G0 GPIO_G0 GPIO_G0 GPIO_G0/SEG16 GPIO_G0 3.10 LOSC/RTC RTC is a 24-bits counter with the following functions; the clock source is LOSC/INTK32. Time Alarm Timer ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor
47、 Co., Ltd 2007. All rights reserved. Ver. 1.1 24/46 2007-3-22 LOSC MUX 16384 24bit up counter REG45 REG46 REG47 Compare REG48 REG49 REG4A 1256 1256 1256 REG4B REG4C REG4D R44_7 INTK32 R44_6 REG43.5 IRQ2Hz REG43.4 REG43.0(over flow flag) REG43.3 load Alarm IRQ REG43.7 REG43.6 RTC Timer IRQ3.11 HOSC/P
48、LL Input: A7:0, DI7:0, IOW-, IOR-, RESET- Output: HCK, PLLCK, CK48MHZ ATJ2063 supports 24Mhz crystal, and it is the system clock source. A low jitter PLL referenced to 24MHz is used to generate clock for DSP and for serial communication protocols such as USB, UART, etc. The clock used in serial comm
49、unications is 48MHz. Another PLL referenced to 24MHz is used to generate ATJ2063 PRODUCT DATASHEET Copyright Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 25/46 2007-3-22 22.5792MHz for sample rate 44.1K/22.05KHz/11.025KHz and 24.576MHz for audio sequence of 48khz. 3.12 PMU/DC-DC The power management unit, PMU, includes: 1. VDD (for core), VCC (for I/O) DC-DC PFM converter 2. VDD regulator 3. RC oscillat
