1、VHDL 程序填空题(一) 在下面横线上填上合适的 VHDL 关键词，完成 2 选 1 多路选择器的设计。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;1 MUX21 ISPORT(SEL:IN STD_LOGIC;A,B:IN STD_LOGIC;Q: OUT STD_LOGIC );END MUX21;2 BHV OF MUX21 ISBEGINQ IF DATAIN=“10“ THEN NST IF DATAIN=“11“ THEN NST IF DATAIN=“01“ THEN NST IF DATAIN=“00“ THEN NSTQOUTQOUTQ
2、OUTNULL;42 ; END IF; END PROCESS; END ART;(十三) 在下面横线上填上合适的语句，完成计数器的设计。说明：设计一个带有异步复位和时钟使能的一位八进制加法计数器（带进位输出端） 。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT8 ISPORT (CLK,RST,EN : IN STD_LOGIC; CQ : OUT STD_LOGIC_VECTOR( 43 DOWNTO 0); COUT : OUT STD_LOGIC ); END CN
3、T8;ARCHITECTURE BEHAV OF CNT8 ISBEGIN PROCESS(CLK, RST, EN)44 CQI : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGINIF RST = 1 THEN CQI := “000”; 45 CLKEVENT AND CLK=1 THEN IF EN = 1 THEN IF CQI POUT POUT POUT POUT POUT POUT POUT POUT POUT POUT POUTZZZZZZZZIF DATAIN=0 THEN PRESENT_STATE:=S1;ELSE PRESENT_STATE:=S
4、0; END IF;WHEN S1=IF DATAIN=1 THEN PRESENT_STATE:=S2;ELSE PRESENT_STATE:=S1; END IF;WHEN S2=IF DATAIN=1 THEN PRESENT_STATE:=S3;ELSE PRESENT_STATE:=S1; END IF;WHEN S3=IF DATAIN=1 THEN PRESENT_STATE:=S4;ELSE PRESENT_STATE:=S1; END IF;WHEN S4=IF DATAIN=1 THEN PRESENT_STATE:=S5;ELSE PRESENT_STATE:=S1; E
5、ND IF;WHEN S5=IF DATAIN=1 THEN PRESENT_STATE:=S6;ELSE PRESENT_STATE:=S1; END IF;WHEN S6=IF DATAIN=1 THEN PRESENT_STATE:=S7;ELSE PRESENT_STATE:=S1; END IF;WHEN S7=IF DATAIN=0 THEN PRESENT_STATE:=S8;QIF DATAIN=0 THEN PRESENT_STATE:= 77 ;ELSE PRESENT_STATE:= 78 ; END IF;END CASE;79 CLK=1;END PROCESS;EN
6、D ART;（二十四）在下面横线上填上合适的语句，完成序列信号发生器的设计。说明：带异步复位为 CLR，时钟端为 CLK，输出端为 Q，串行输出指定序列（低位先出） 。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SENQGEN ISPORT(CLR,CLK:IN STD_LOGIC;Q:OUT STD_LOGIC);END SENQGEN;ARCHITECTURE BEHA OF SENQGEN ISSIGNAL Q_TE
7、MP:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINPROCESS(CLK,CLR)BEGINIF CLR=1 THEN Q_TEMPQQQQQQQQ 83 ;END CASE;END PROCESS;END BEHA;（二十五）在下面横线上填上合适的语句，完成七人表决器的设计。说明：一个带输出显示的七人表决器(两种结果：同意，反对)。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY BIAOJUE7 ISPORT(D:IN STD_LOGIC_VECTOR(0 TO 6);RLED,GLED:OUT STD_LOGIC;LE
8、DSEG:OUT STD_LOGIC_VECTOR( 6 DOWNTO 0);END; ARCHITECTURE BEV OF BIAOJUE7 ISBEGIN PROCESS(D) VARIABLE COUNT:INTEGER RANGE 0 TO 7 ;BEGIN COUNT:= 84 ;FOR 85 LOOP IF D(I)=1 THEN COUNT:= 86 ;ELSE COUNT:=COUNT;END IF;END LOOP;IF COUNT 87 THEN GLED LEDSEG LEDSEG LEDSEG LEDSEG LEDSEG LEDSEG LEDSEG LEDSEG OU
9、TPUTS OUTPUTS OUTPUTS OUTPUTS 105 , D= 106 ,Q= 107 ,QB= 108 );END GENERATE;END RPLCONT;（三十一）在下面横线上填上合适的语句，完成交通灯控制器的设计。说明：红、黄、绿灯分别亮 10 秒，状态 0 时东西绿灯亮，南北红灯亮；状态 1 时东西绿、黄灯亮，南北红灯亮；状态 2 时东西红灯亮，南北绿灯亮；状态 3 时东西红灯亮，南北绿、黄灯亮。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY TRAFFICL
10、ED1 ISPORT (CLK, RESET: IN STD_LOGIC;Q: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) );END;ARCHITECTURE ONE OF TRAFFICLED1 IS SIGNAL Y_EWSN, G_EWSN, R_EWSN:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL COUNT:INTEGER RANGE 0 TO 9;SIGNAL STATE:INTEGER RANGE 0 TO 3;BEGIN PROCESS(RESET, CLK,COUNT)BEGINIF RESET=1 THEN COUNT
11、110 THEN STATE Y_EWSN Y_EWSN Y_EWSN Y_EWSN 111 ;END CASE;END PROCESS;Q(0) 0 );DATAOUT( OTHERS = 0 );FOR I IN 0 TO 15 LOOPDATA ( I ) 115 ;END LOOP;ELSIF CLKEVENT AND CLK = 1 THENIF PUSH = 1 AND POP= 0 THEN - PUSHFOR I IN 0 TO 14 LOOPDATA ( I ) 116 ;END LOOP;DATA (15) 117 ;STACKFLAG1 ELSIF PUSH = 0 AN
12、D POP= 1 THEN - POPDATAOUTDATA (15);FOR I IN 15 DOWNTO 1 LOOPDATA ( I ) 118 ;END LOOP；STACKFLAGSTACKFLAG ( 119 DOWNTO 0 ) END IF；END IF；END PROCESS;END A;（三十四）在下面横线上填上合适的语句，完成一个 8 位分频器的设计。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY PULSE ISPORT ( CLK : IN STD_LOGI
13、C;D : IN STD_LOGIC_VECTOR (7 DOWNTO 0);FOUT : OUT STD_LOGIC );END;ARCHITECTURE ONE OF PULSE ISSIGNAL FULL : STD_LOGIC;BEGINP_REG: PROCESS(CLK)120 CNT8 : STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINIF CLKEVENT AND CLK = 1 THENIF CNT8 = “11111111“ THEN CNT8 := 121 ; -当CNT8计数计满时，输入数据D被同步预置给计数器CNT8FULL IF INA = “
14、00” THEN N_ST IF INA = “00” THEN N_ST IF INA = “11” THEN N_ST IF INA = “11” THEN N_ST N_ST = ST0;END CASE;END PROCESS;END ONE;（三十七）在下面横线上填上合适的语句，完成下参数可定制带计数使能异步复位计数器的 VHDL 设计。- N-BIT UP COUNTER WITH LOAD, COUNT ENABLE, AND- ASYNCHRONOUS RESETLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGI
15、C_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY COUNTER_N IS134 (WIDTH : INTEGER := 8);PORT(DATA : IN STD_LOGIC_VECTOR (WIDTH-1DOWNTO 0);LOAD, EN, CLK, RST : IN STD_LOGIC;Q : OUT STD_LOGIC_VECTOR ( 135 DOWNTO 0);END COUNTER_N;ARCHITECTURE BEHAVE OF COUNTER_N ISSIGNAL COUNT : STD_LOGIC_VECTOR (WID
16、TH-1 DOWNTO 0);BEGINPROCESS(CLK, RST)BEGINIF RST = 1 THENCOUNT = 136 ; 清零ELSIF CLKEVENT AND CLK = 1 THEN 边沿检测IF LOAD = 1 THENCOUNT = DATA;137 EN = 1 THENCOUNT = COUNT + 1;END 138 ;END IF;END PROCESS;Q = COUNT;END BEHAVE;（三十八）在下面横线上填上合适的语句，完成下图所示 RTL 原理图的 VHDL 设计。LIBARRY IEEE;USE IEEE.STD_LOGIC_1164.
17、ALL;ENTITY MYCIR IS PORT ( XIN, CLK : IN STD_LOGIC;YOUT : OUT STD_LOGIC);END MYCIR;ARCHITECTURE ONE OF MYCIR ISSIGNAL A, B, C;BEGINB = XIN OR 139 ;PROCESS (CLK)BEGINIF CLKEVENT AND CLK = 1 THENA = 140 ;C = 141 ;END IF;END PROCESS;YOUT = C;END ONE;（三十九）在下面横线上填上合适的语句，完成下图所示 RTL 原理图的 VHDL 设计。LIBRARY IE
18、EE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MYCIR ISPORT (A, CLK : IN STD_LOGIC;C, B : OUT STD_LOGIC );END MYCIR;ARCHITECTURE BEHAV OF MYCIR ISSIGNAL TA : STD_LOGIC;BEGINPROCESS (A, CLK)BEGINIF CLKEVENT AND CLK = 1 THENTA = A;B = 142 ;C = 143 ;END IF;END PROCESS;END BEHAV;（四十）在下面横线上填上合适的语句，完成下图所示 RTL 原理图的
19、 VHDL 设计。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MYCIR ISPORT (AIN , BIN , CLK : IN STD_LOGIC;COUT : OUT STD_LOGIC);END MYCIR;ARCHITECTURE ONE OF MYCIR ISSIGNAL TB, TC;BEGINPROCESS (CLK) BEGINIF CLKEVENT AND CLK = 1 THENTB = BIN;END IF;END PROCESS;PROCESS (CLK, TC) BEGINIF CLK = 1 THEN COUT = 144 ;END IF;END PROCESS;TC = AIN XOR 145 ;END ONE;（四十一）在下面横线上填上合适的语句，完成简易彩灯控制电路的 VHDL 设计。说明: 该控制电路控制红、绿、黄三个发光管循环发亮。要求红发光管亮 2 秒，绿发光管亮 3 秒，黄发光管亮 1 秒。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ASM_LED IS
